Patents Assigned to Tower Semiconductor Ltd.
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Patent number: 11979676Abstract: A robust analog counter that may include an output capacitor having a first capacitance, and a charging unit (CU) that is configured to determine that an event to be counted occurred, and charge the output capacitor at a first current and during a output capacitor charging period, wherein a duration of the output capacitor charging period is proportional to the first capacitance, thereby increasing an output voltage of the output capacitor by a voltage quote that is indifferent to at least one out of process variation, temperature or power supply voltage value.Type: GrantFiled: April 26, 2022Date of Patent: May 7, 2024Assignee: TOWER SEMICONDUCTOR LTD.Inventors: Raz Reshef, Dmitry Dain
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Patent number: 11962919Abstract: For example, analog pixel circuitry may include a first input to input an analog pixel signal of the pixel; Sample and Hold (SH) circuitry to provide an analog sample of the pixel based on the analog pixel signal; one or more second inputs to input analog samples of one or more binning pixels, respectively; a plurality of capacitors having capacitor outputs connected to a common output terminal, wherein a capacitor input of a first capacitor is connected to an input terminal to input the analog sample of the pixel from the SH circuitry, wherein capacitor inputs of one or more second capacitors are connected to the one or more second inputs, respectively; and an amplifier configured to provide an amplified analog signal by amplifying an analog signal from the common output terminal.Type: GrantFiled: July 24, 2022Date of Patent: April 16, 2024Assignee: TOWER SEMICONDUCTOR LTD.Inventors: Alexander Faingersh, Vered Antebi, Raz Reshef
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Publication number: 20240063038Abstract: A location detection system for detecting a location of a wafer within a transfer robot vacuum chamber (TRVC), the detection system may include (i) an illumination unit that is configured to direct a transmitted radiation pattern through a transparent window of the TRVC and towards one or more TRVS reflecting elements located below an upper side of a wafer holding element of the transfer robot; wherein the illumination unit is located outside the TRVC; (ii) a sensing unit that is configured to generate one or more detection signals indicative of a received radiation pattern that is reflected from the one or more TRVS reflecting elements; and (iii) a location processing circuit that is configured to detect a location of the wafer based on the one or more detection signals.Type: ApplicationFiled: August 21, 2022Publication date: February 22, 2024Applicant: Tower Semiconductor Ltd.Inventors: Slava Superfine, Yaniv Malachy, Dany Trabelsi
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Publication number: 20240031693Abstract: For example, analog pixel circuitry may include a first input to input an analog pixel signal of the pixel; Sample and Hold (SH) circuitry to provide an analog sample of the pixel based on the analog pixel signal; one or more second inputs to input analog samples of one or more binning pixels, respectively; a plurality of capacitors having capacitor outputs connected to a common output terminal, wherein a capacitor input of a first capacitor is connected to an input terminal to input the analog sample of the pixel from the SH circuitry, wherein capacitor inputs of one or more second capacitors are connected to the one or more second inputs, respectively; and an amplifier configured to provide an amplified analog signal by amplifying an analog signal from the common output terminal.Type: ApplicationFiled: July 24, 2022Publication date: January 25, 2024Applicant: TOWER SEMICONDUCTOR LTD.Inventors: Alexander Faingersh, Vered Antebi, Raz Reshef
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Patent number: 11843043Abstract: A method fabricating a GaN based sensor including: forming a gate dielectric layer over a GaN hetero-structure including a GaN layer formed over a substrate and a first barrier layer formed over the GaN layer; forming a first mask over the gate dielectric layer; etching the gate dielectric layer and the first barrier layer through the first mask, thereby forming source and drain contact openings; removing the first mask; forming a metal layer over the gate dielectric layer, wherein the metal layer extends into the source and drain contact openings; forming a second mask over the metal layer; etching the metal layer, the gate dielectric layer and the GaN heterostructure through the second mask, wherein a region of the GaN heterostructure is exposed; and thermally activating the metal layer in the source and drain contact openings. The gate dielectric may exhibit a sloped profile, and dielectric spacers may be formed.Type: GrantFiled: November 4, 2021Date of Patent: December 12, 2023Assignee: Tower Semiconductor Ltd.Inventors: Ruth Shima-Edelstein, Ronen Shaul, Roy Strul, Anatoly Sergienko, Liz Poliak, Ido Gilad, Alex Sirkis, Yakov Roizin
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Publication number: 20230345149Abstract: A robust analog counter that may include an output capacitor having a first capacitance, and a charging unit (CU) that is configured to determine that an event to be counted occurred, and charge the output capacitor at a first current and during a output capacitor charging period, wherein a duration of the output capacitor charging period is proportional to the first capacitance, thereby increasing an output voltage of the output capacitor by a voltage quote that is indifferent to at least one out of process variation, temperature or power supply voltage value.Type: ApplicationFiled: April 26, 2022Publication date: October 26, 2023Applicant: Tower Semiconductor Ltd.Inventors: Raz Reshef, Dmitry Dain
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Publication number: 20230332947Abstract: A UVC disinfection system that may include a UVC radiation illumination unit, a control unit, and a node. The node may include (i) a power supply, (ii) a UVC dose sensing unit that comprises a UVC sensing element, wherein the UVC dose sensing unit is configured to sense that the UVC radiation dose received by the node reached a predefined UVC radiation dose; and (iii) a node transmitter that is configured transmit a node unique signal following a sensing, by the UVC dose sensing unit, that the UVC radiation dose received by the node reached a predefined UVC radiation dose. The control unit is configured to control an emission of UVC radiation from the UVC radiation illumination unit based on a reception or a lack of reception of the node unique signal.Type: ApplicationFiled: April 13, 2022Publication date: October 19, 2023Applicant: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Pikhay Evgeny, Michael Yampolsky
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Publication number: 20230268363Abstract: A method for manufacturing optical unit, the method includes (a) obtaining an intermediate optical unit that comprises a semiconductor portion, a transparent organic layer, the array of organic microlenses and a protective layer; (b) depositing a protective mask above a first protective layer region; (c) removing, by applying a first etch process, the second protective layer region to expose a second region of the transparent organic layer; and (d) removing, by applying a second etch process, the second region of the transparent organic layer to expose the contact pads and removing the protective mask while maintaining the first protective layer portion.Type: ApplicationFiled: February 22, 2022Publication date: August 24, 2023Applicant: Tower Semiconductor Ltd.Inventors: Naor INBAR, Omer KATZ, Tzur MILLER, Ayala ELKAYAM
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Publication number: 20230238070Abstract: A semiconductor device includes a storage element write unit including a storage element configured to be electrically written only once and store two values, a write controller connected to the storage element through a first node signal and configured to perform a write to the storage element based on a write control signal instructing a write to the storage element, and a write state detection circuit configured to detect that the storage element is in a write state based on a measurement signal obtained by measuring the first node signal. In a case where the write controller receives a detection signal indicating that the storage element is in the write state from the write state detection circuit after start of a write to the storage element, the write controller stops write operation after a lapse of a predetermined time from detection of the write state of the storage element.Type: ApplicationFiled: March 14, 2023Publication date: July 27, 2023Applicants: TOWER PARTNERS SEMICONDUCTOR CO., LTD., TOWER SEMICONDUCTOR LTD.Inventors: Hiroshige HIRANO, Hiroaki KURIYAMA, Masahiko SAKAGAMI, Micha GUTMAN, Erez SARIG, Yakov ROIZIN
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Patent number: 11698299Abstract: A UV radiation sensor that includes an area that is filled with a dielectric material, the area comprises a first portion of a first thickness and a second trench portion with dielectric of a second thickness, wherein the first thickness is smaller than the second thickness; a floating gate that comprises a first floating gate portion that is positioned above the first area portion and a second floating gate portion that is positioned above the trench portion, wherein the second floating gate portion comprises multiple segments, wherein there are one or more gaps between two or more of the multiple segments; a charging element for charging the floating gate; and a readout element for reading the floating gate.Type: GrantFiled: August 5, 2021Date of Patent: July 11, 2023Assignee: TOWER SEMICONDUCTOR LTD.Inventors: Pikhay Evgeny, Yakov Roizin, Michael Yampolsky
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Publication number: 20230200062Abstract: A semiconductor device includes a memory cell on a semiconductor substrate. The memory cell includes a memory element, a first assistance element, and a second assistance element. The memory element includes a source region and a drain region, and a selection gate and a floating gate in series therebetween. The first assistance element includes a first impurity region and a first gate. The second assistance element includes a second impurity region and a second gate. The first and second gates are electrically connected to the floating gate. The second impurity region is connected to a signal line that is connected to the drain region or a signal line that is connected to the selection gate.Type: ApplicationFiled: May 27, 2022Publication date: June 22, 2023Applicants: TOWER PARTNERS SEMICONDUCTOR CO., LTD., TOWER SEMICONDUCTOR LTD.Inventors: Hiroshige HIRANO, Hiroaki KURIYAMA, Atsushi NOMA
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Patent number: 11644580Abstract: A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.Type: GrantFiled: April 14, 2022Date of Patent: May 9, 2023Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Evgeny Pikhay, Vladislav Dayan
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Publication number: 20230071740Abstract: A solid-state imaging device includes a pixel array where pixels are arranged in a matrix. Each of the pixels includes a photoelectric conversion unit configured to generate a signal charge based on incident light, and an element isolation layer having light-shielding properties and surrounding a periphery of the photoelectric conversion unit. The element isolation layers of adjacent ones of the pixels in a row direction and a column direction are isolated from each other. A charge storage layer and a charge trapping layer are provided in each of regions between the element isolation layers of the adjacent ones of the pixels in the row direction and the column direction. The charge storage layer stores the signal charge. The charge trapping layer reduces incidence of light on the charge storage layer.Type: ApplicationFiled: May 28, 2021Publication date: March 9, 2023Applicants: TOWER PARTNERS SEMICONDUCTOR CO., LTD., TOWER SEMICONDUCTOR LTD.Inventor: Masafumi TSUTSUI
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Patent number: 11592584Abstract: There may be provided a radiation sensor, that may include multiple semiconductor regions that form a sensing PN junction and a draining PN junction that is located below the sensing PN junction; a bias circuit that is configured to (i) bias the sensing PN junction to maintain a sensing PN junction depletion region of a fixed size during a first sensing period and during a second sensing period, and (i) bias the draining PN junction to form a draining PN junction depletion region of a first size during the first sensing period and of a second size during the second sensing period; and an output circuit that is configured to generate a first output signal that represent sensed radiation out of radiation that impinged on the radiation sensor during the first sensing period, and to generate a second output signal that represent sensed radiation out of radiation impinged on the radiation sensor during the second sensing period.Type: GrantFiled: August 5, 2021Date of Patent: February 28, 2023Assignee: Tower Semiconductor Ltd.Inventor: Amos Fenigstein
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Publication number: 20230059212Abstract: A solid-state imaging device includes an N-type semiconductor layer, an element layer including a photoelectric conversion element and an active element, an interconnect layer providing an interconnect for the active element, and an element isolation trench penetrating the semiconductor layer. The element layer includes a P-type region and an N-type region. A first hole storage layer is formed on a surface of the semiconductor layer on a side opposite to the element layer. A second hole storage layer is formed in contact portions of the semiconductor layer and the element layer with the element isolation trench. The P-type region of the element layer and the first hole storage layer are connected to each other by the second hole storage layer.Type: ApplicationFiled: February 19, 2021Publication date: February 23, 2023Applicants: TOWER PARTNERS SEMICONDUCTOR CO., LTD., TOWER SEMICONDUCTOR LTD.Inventors: Masahiro ODA, Hiroki TAKAHASHI, Hiroyuki DOI, Hirohisa OTSUKI
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Publication number: 20230042154Abstract: There may be provided a radiation sensor, that may include multiple semiconductor regions that form a sensing PN junction and a draining PN junction that is located below the sensing PN junction; a bias circuit that is configured to (i) bias the sensing PN junction to maintain a sensing PN junction depletion region of a fixed size during a first sensing period and during a second sensing period, and (i) bias the draining PN junction to form a draining PN junction depletion region of a first size during the first sensing period and of a second size during the second sensing period; and an output circuit that is configured to generate a first output signal that represent sensed radiation out of radiation that impinged on the radiation sensor during the first sensing period, and to generate a second output signal that represent sensed radiation out of radiation impinged on the radiation sensor during the second sensing period.Type: ApplicationFiled: August 5, 2021Publication date: February 9, 2023Applicant: Tower Semiconductor Ltd.Inventor: Amos Fenigstein
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Publication number: 20230022648Abstract: A biosensor that includes a semiconductor active region; a sensing region configured to contact a fluid; and multiple electrodes that comprise decoupling electrodes and additional electrodes. The decoupling electrodes may be configured, wherein operating in a first mode, to prevent a formation of a top conductive channel within the semiconductor active region; and wherein the additional electrodes are configured, wherein operating in the first mode, to independently control (i) one or more properties of one or more other conductive channels formed within the semiconductor active region, and (ii) a Debye length at an interface between the sensing region and the fluid.Type: ApplicationFiled: July 14, 2021Publication date: January 26, 2023Applicants: Tower Semiconductor Ltd., B.G. Negev Technologies and Applications Ltd., at Ben-Gurion UniversityInventors: Gil Shalev, Yakov Roizin, Pikhay Evgeny, Ie Mei Bhattacharyya, Izhar Ron, Doron Greental
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Patent number: 11543290Abstract: An ultraviolet sensor that may include a group of serially connected photovoltaic diodes of alternating polarities; a selective blocking portion that is configured to prevent ultraviolet radiation from reaching photovoltaic diodes that belong to the group and are of a first polarity, while allowing the ultraviolet radiation to reach photovoltaic diodes that belong to the group and are of a second polarity; and an interface for providing an output signal of the group, the output signal is indicative of ultraviolet radiation sensed by the photovoltaic diodes that belong to the group and are of the second polarity.Type: GrantFiled: July 14, 2020Date of Patent: January 3, 2023Assignee: TOWER SEMICONDUCTOR LTD.Inventors: Yakov Roizin, Pikhay Evgeny
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Patent number: 11522079Abstract: An electrostatically controlled sensor includes a GaN/AlGaN heterostructure having a 2DEG channel in the GaN layer. Source and drain contacts are electrically coupled to the 2DEG channel through the AlGaN layer. A gate dielectric is formed over the AlGaN layer, and gate electrodes are formed over the gate dielectric, wherein each gate electrode extends substantially entirely between the source and drain contacts, wherein the gate electrodes are separated by one or more gaps (which also extend substantially entirely between the source and drain contacts). Each of the one or more gaps defines a corresponding sensing area between the gate electrodes for receiving an external influence. A bias voltage is applied to the gate electrodes, such that regions of the 2DEG channel below the gate electrodes are completely depleted, and regions of the 2DEG channel below the one or more gaps in the direction from source to drain are partially depleted.Type: GrantFiled: October 16, 2019Date of Patent: December 6, 2022Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Victor Kairys, Ruth Shima-edelstein
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Patent number: 11411495Abstract: Some demonstrative embodiments include a Metal-Oxide-Semiconductor (MOS) transistor including a split-gate structure. For example, an Integrated Circuit (IC) may include a MOS including a body; a source; a drain; and a split-gate structure including a control gate and at least one voltage-controlled Field-Plate (FP), the control gate is between the source and the voltage-controlled FP, the voltage-controlled FP is between the control gate and the drain, the control gate configured to switch the MOS transistor between an on state and an off state according to a switching voltage; and a voltage controller configured to apply a variable control voltage to the voltage-controlled FP, the variable control voltage based on at least one control parameter, the at least one control parameter including at least one of a load current driven by the MOS transistor or a switching frequency of the switching voltage.Type: GrantFiled: June 23, 2020Date of Patent: August 9, 2022Assignee: TOWER SEMICONDUCTOR LTD.Inventor: Erez Sarig