Patents Assigned to Tower Semiconductor Ltd.
  • Patent number: 12617562
    Abstract: An apparatus may include a processor configured to process photodiode signal information, which corresponds to a plurality of photodiodes of an aerial vehicle, for example, to identify a plurality of electric currents, which may be generated by the plurality of photodiodes based on energy of a light beam to charge a battery of the aerial vehicle. The processor may be configured to determine a vehicle-position displacement to displace the aerial vehicle based on the plurality of electric currents. The vehicle-position displacement may be configured to adjust a photodiode-beam relative position of the plurality of photodiodes relative to the light beam. The apparatus may include an output to provide position displacement information based on the vehicle-position displacement.
    Type: Grant
    Filed: March 7, 2024
    Date of Patent: May 5, 2026
    Assignee: TOWER SEMICONDUCTOR LTD.
    Inventors: Yakov Roizin, Evgeny Pikhay, Niv Mizrahi
  • Publication number: 20260120767
    Abstract: A semiconductor memory device includes a plurality of memory cells formed on a semiconductor substrate. Each of the memory cells includes a first floating gate transistor (TFG1), a second floating gate transistor (TFG2), a first erasing element, a second erasing element, and a memory cell selection transistor. A gate of TFG1 is electrically coupled to a gate of the first erasing element. A gate of TFG2 is electrically coupled to a gate of the second erasing element. A source of TFG1 is electrically coupled to a drain of the memory cell selection transistor. A source of TFG2 is electrically coupled to the drain of the memory cell selection transistor or a drain of TFG1.
    Type: Application
    Filed: December 30, 2024
    Publication date: April 30, 2026
    Applicants: TOWER PARTNERS SEMICONDUCTOR CO., LTD., TOWER SEMICONDUCTOR LTD.
    Inventors: Hiroshige HIRANO, Hiroaki KURIYAMA, Atsushi NOMA, Evgeny PIKHAY, Yakov ROIZIN
  • Publication number: 20260123429
    Abstract: A semiconductor device includes a semiconductor substrate, an interlayer insulating film and an element region formed on the semiconductor substrate, and first and second seal rings surrounding the element region. Each of the first and second seal rings is formed of a layered conductive film including at least one linear interconnect layer and at least one linear via layer, and are insulated from each other or electrically connected only in an uppermost one of layers forming the conductive film. The first seal ring is electrically insulated from the semiconductor substrate. The second seal ring is electrically connected to the semiconductor substrate.
    Type: Application
    Filed: February 3, 2025
    Publication date: April 30, 2026
    Applicants: TOWER PARTNERS SEMICONDUCTOR CO., LTD., TOWER SEMICONDUCTOR LTD.
    Inventors: Hiroshige HIRANO, Yutaka ITO, Hiroaki KURIYAMA
  • Publication number: 20260013267
    Abstract: A robust near infrared sensing device and method for operating of robust near infrared device, the method includes (i) exposing a first side edge of the device to near infrared (NIR) radiation; (ii) detecting by a NIR PIN diode (NPD), the NIR radiation, while operating at a fully depletion mode, (iii) collecting, by guard PIN diodes positioned at different sides of the NPD and while operating in the fully depletion mode, electron-hole pairs generated by unwanted radiation from any side of different sides of the near infrared PIN diode, and preventing these electron-hole pairs from any side of NPD to reach the NPD.
    Type: Application
    Filed: July 2, 2024
    Publication date: January 8, 2026
    Applicant: Tower Semiconductor Ltd.
    Inventors: Yakov Roizin, Pikhay Evgeny, Niv Mizrahi
  • Publication number: 20260011687
    Abstract: For example, a sensor die may include a plurality of pixel sensors configured to sense ionizing radiation. The plurality of pixel sensors may include a plurality of detection diodes. For example, the plurality of detection diodes may be in a surface region of a silicon substrate of the sensor die. The plurality of detection diodes may be formed of a diode material. For example, the sensor die may include a plurality of dummy-diode diffusions in the surface region of the silicon substrate. The plurality of dummy-diode diffusions may be in a plurality of gettering regions between the plurality of detection diodes. The plurality of dummy-diode diffusions may include the diode material. For example, a width of the dummy-diode diffusion may be no more than 5 percent of a width of a detection diode of the two adjacent detection diodes.
    Type: Application
    Filed: July 7, 2024
    Publication date: January 8, 2026
    Applicant: TOWER SEMICONDUCTOR LTD.
    Inventors: Ruth Shima-Edelstein, Yakov Roizin, Avi Strum
  • Publication number: 20260013237
    Abstract: A radiation sensing device, that includes a sensing region that includes a radiation sensor, and an exterior region that includes a first guard element, a field limiting region, an array of surface holes and one or more sub-surface inner spaces. The exterior region is configured to prevent breakdown of the radiation sensing device at a presence of a surface charge created due to the radiation. The array of surface holes and the sub-surface inner spaces are located between the first guard element and the field limiting region and are configured to reduce the capacitance pf the exterior region.
    Type: Application
    Filed: July 2, 2024
    Publication date: January 8, 2026
    Applicant: Tower Semiconductor Ltd.
    Inventors: Ruth Shima-Edelstein, Yakov Roizin
  • Publication number: 20260009677
    Abstract: A NIR spectrometry device that includes different NIR PIN diodes (NPDs) and a guard PIN diode (VLPD) that are operated in a fully depletion mode. The different NPDs are located at different lateral positions corresponding to absorption depths of different NIR wavelengths. Each NPD is configured to collect electron-hole pairs (EHPs) generated by radiation that passes through a side edge of the device at a wavelength having an absorption depth that corresponds to a lateral position of the NPD. The VLPD is located at a lateral position that corresponds to a distance from the side edge that exceeds an absorption depth of visible light. The VLPD is configured to collect EHPs generated by unwanted radiation that passed through the side edge of the NIR spectrometry device and to prevent the EHPs generated by unwanted radiation to reach any of the different NPDs.
    Type: Application
    Filed: July 2, 2024
    Publication date: January 8, 2026
    Applicant: Tower Semiconductor Ltd.
    Inventors: Pikhay Evgeny, Niv Mizrahi, Yakov Roizin
  • Publication number: 20250366225
    Abstract: For example, a radiation detector may include a bonded die including a plurality of active pixel sensors configured to sense ionizing radiation. For example, the bonded die may include a detection die including a plurality of detection diodes. For example, an active pixel sensor of the plurality of active pixel sensors may include a detection diode of the plurality of detection diodes to generate an electric detection signal based on detected ionized radiation detected by the detection diode. For example, the bonded die may include an electronic-circuitry die bonded to the detection die. For example, a thickness of the electronic-circuitry die may be less than 4 percent of a thickness of the detection die. For example, the electronic-circuitry die may include a plurality of transistors. For example, the active pixel sensor may include one or more transistors of the plurality of transistors to amplify the electronic detection signal.
    Type: Application
    Filed: May 26, 2024
    Publication date: November 27, 2025
    Applicant: TOWER SEMICONDUCTOR LTD.
    Inventors: Yakov Roizin, Evgeny Pikhay, Inna Shehter, Avi Strum
  • Publication number: 20250329528
    Abstract: There is provided a method that includes (i) removing organic polymer residuals formed on a dry-etched hole that leads to a semiconductor structural element and coating the dry-etched hole with a non-organic polymer to provide a coated hole by exposing the dry-etched hole to a gaseous mixture, the gaseous mixture includes a fluorine based chemical compound, before the removing, the dry-etched hole was least partially coated with dry-etch residuals that comprise the organic polymer residuals; and (ii) coating the coated hole and removing fluorine based chemical compound residuals to provide an additionally coated hole by exposing the first coated hole to a nitrogen based plasma.
    Type: Application
    Filed: April 18, 2024
    Publication date: October 23, 2025
    Applicant: Tower Semiconductor Ltd.
    Inventors: Alex Sirkis, Julian Guzman, Carlo Romano, Simone Marchetti
  • Patent number: 12432915
    Abstract: A semiconductor device includes a memory cell on a semiconductor substrate. The memory cell includes a memory element, a first assistance element, and a second assistance element. The memory element includes a source region and a drain region, and a selection gate and a floating gate in series therebetween. The first assistance element includes a first impurity region and a first gate. The second assistance element includes a second impurity region and a second gate. The first and second gates are electrically connected to the floating gate. The second impurity region is connected to a signal line that is connected to the drain region or a signal line that is connected to the selection gate.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: September 30, 2025
    Assignees: TOWER PARTNERS SEMICONDUCTOR CO., LTD., TOWER SEMICONDUCTOR LTD.
    Inventors: Hiroshige Hirano, Hiroaki Kuriyama, Atsushi Noma
  • Patent number: 12419119
    Abstract: A solid-state imaging device includes an N-type semiconductor layer, an element layer including a photoelectric conversion element and an active element, an interconnect layer providing an interconnect for the active element, and an element isolation trench penetrating the semiconductor layer. The element layer includes a P-type region and an N-type region. A first hole storage layer is formed on a surface of the semiconductor layer on a side opposite to the element layer. A second hole storage layer is formed in contact portions of the semiconductor layer and the element layer with the element isolation trench. The P-type region of the element layer and the first hole storage layer are connected to each other by the second hole storage layer.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: September 16, 2025
    Assignees: TOWER PARTNERS SEMICONDUCTOR CO., LTD., TOWER SEMICONDUCTOR LTD.
    Inventors: Masahiro Oda, Hiroki Takahashi, Hiroyuki Doi, Hirohisa Otsuki
  • Publication number: 20250282503
    Abstract: For example, an apparatus may include a processor configured to process photodiode signal information, which corresponds to a plurality of photodiodes of an aerial vehicle, for example, to identify a plurality of electric currents, which may be generated by the plurality of photodiodes based on energy of a light beam to charge a battery of the aerial vehicle. For example, the processor may be configured to determine a vehicle-position displacement to displace the aerial vehicle based on the plurality of electric currents. For example, the vehicle-position displacement may be configured to adjust a photodiode-beam relative position of the plurality of photodiodes relative to the light beam. For example, the apparatus may include an output to provide position displacement information based on the vehicle-position displacement.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 11, 2025
    Applicant: TOWER SEMICONDUCTOR LTD.
    Inventors: Yakov Roizin, Evgeny Pikhay, Niv Mizrahi
  • Patent number: 12353012
    Abstract: A method for manufacturing an optical system, the method includes obtaining an intermediate semiconductor item that comprises a silicon substrate and a stack of layers that comprises a monocrystalline silicon layer and is positioned between two silicon alloy layers; wherein the silicon substrate comprises diffusion regions; and performing Complementary Metal-Oxide-Semiconductor (CMOS) compliant operations to provide, based on the intermediate semiconductor item, a first switching cell that is formed on the silicon substrate.
    Type: Grant
    Filed: August 30, 2024
    Date of Patent: July 8, 2025
    Assignee: Tower Semiconductor Ltd.
    Inventors: Yakov Roizin, Avi Strum
  • Patent number: 12353017
    Abstract: An optical switching system, including a silicon substrate; a first switching cell that is formed on the silicon substrate, wherein the first switching cell includes first till thirs ports, a monocrystalline silicon waveguide (MSW) that comprises a first MSW segment and a second MSW segment; and an actuation unit that is configured to move each one of the first MSW segment and the second MSW segment between at least three different positions thereby determining whether an optical signal received at the first port is (a) directed through the MSW to the second port, or (b) is directed to the third port through a first bus waveguide.
    Type: Grant
    Filed: August 30, 2024
    Date of Patent: July 8, 2025
    Assignee: Tower Semiconductor Ltd.
    Inventors: Yakov Roizin, Avi Strum
  • Patent number: 12341337
    Abstract: For example, a multi voltage-domain Electro Static Discharge (ESD) power clamp may include a plurality of pins; and an ESD array including a cascaded plurality of ESD power clamps. For example, the ESD array may include a plurality of ESD array portions configured to protect a respective plurality of voltage domains from ESD. For example, the ESD array may be configured to connect the plurality of ESD array portions between a respective plurality of pin pairs from the plurality of pins. For example, an ESD array portion corresponding to a voltage domain may include one or more ESD power clamps of the cascaded plurality of ESD power clamps. For example, the ESD array portion may be configured to protect a voltage range of the voltage domain.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: June 24, 2025
    Assignee: TOWER SEMICONDUCTOR LTD.
    Inventors: Efraim Aharoni, Avi Parvin, Roda Kanawati, Allon Parag, Einat Arad Ophir
  • Patent number: 12332115
    Abstract: A UVC disinfection system that may include a UVC radiation illumination unit, a control unit, and a node. The node may include (i) a power supply, (ii) a UVC dose sensing unit that comprises a UVC sensing element, wherein the UVC dose sensing unit is configured to sense that the UVC radiation dose received by the node reached a predefined UVC radiation dose; and (iii) a node transmitter that is configured transmit a node unique signal following a sensing, by the UVC dose sensing unit, that the UVC radiation dose received by the node reached a predefined UVC radiation dose. The control unit is configured to control an emission of UVC radiation from the UVC radiation illumination unit based on a reception or a lack of reception of the node unique signal.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: June 17, 2025
    Assignee: Tower Semiconductor Ltd.
    Inventors: Yakov Roizin, Pikhay Evgeny, Michael Yampolsky
  • Publication number: 20250130213
    Abstract: A sensing device that includes (a) an image sensor matrix that comprises a first pixel and a second pixel; wherein the first pixel is configured to generate a first detection signal indicative of a presence of a first analyte; wherein the second pixel is configured to generate a second detection signal that is indifferent to the presence of the first analyte; and (b) a processing circuit that is configured to determine the presence of the first analyte based on at least a relationship between the first detection signal and the second detection signal.
    Type: Application
    Filed: August 29, 2024
    Publication date: April 24, 2025
    Applicants: Tower Semiconductor Ltd., Fraunhofer Gesellschaft zur Förderung der Angewandten Forschung
    Inventors: Ruth Shima Edelstein, Dmitry Ivanov, Dmitry Veinger, Yakov Roizin, Sonja Hoffmann, Michael Henfling, Sabine Trupp
  • Patent number: 12266670
    Abstract: A method for manufacturing optical unit, the method includes (a) obtaining an intermediate optical unit that comprises a semiconductor portion, a transparent organic layer, the array of organic microlenses and a protective layer; (b) depositing a protective mask above a first protective layer region; (c) removing, by applying a first etch process, the second protective layer region to expose a second region of the transparent organic layer; and (d) removing, by applying a second etch process, the second region of the transparent organic layer to expose the contact pads and removing the protective mask while maintaining the first protective layer portion.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: April 1, 2025
    Assignee: Tower Semiconductor Ltd.
    Inventors: Naor Inbar, Omer Katz, Tzur Miller, Ayala Elkayam
  • Patent number: 12260922
    Abstract: A semiconductor device includes a storage element write unit including a storage element configured to be electrically written only once and store two values, a write controller connected to the storage element through a first node signal and configured to perform a write to the storage element based on a write control signal instructing a write to the storage element, and a write state detection circuit configured to detect that the storage element is in a write state based on a measurement signal obtained by measuring the first node signal. In a case where the write controller receives a detection signal indicating that the storage element is in the write state from the write state detection circuit after start of a write to the storage element, the write controller stops write operation after a lapse of a predetermined time from detection of the write state of the storage element.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: March 25, 2025
    Assignees: TOWER PARTNERS SEMICONDUCTOR CO., LTD., TOWER SEMICONDUCTOR LTD.
    Inventors: Hiroshige Hirano, Hiroaki Kuriyama, Masahiko Sakagami, Micha Gutman, Erez Sarig, Yakov Roizin
  • Publication number: 20240204023
    Abstract: A solid-state imaging device includes a plurality of pixels arrayed in a two-dimensional matrix on a substrate. Each of the pixels includes a light receiving potion that performs photoelectric conversion, a microlens that condenses light to the light receiving potion, and at least one light scattering structure provided between the light receiving potion and the microlens.
    Type: Application
    Filed: December 13, 2023
    Publication date: June 20, 2024
    Applicants: TOWER PARTNERS SEMICONDUCTOR CO., LTD., TOWER SEMICONDUCTOR LTD.
    Inventors: Yoshiaki NISHI, Toshifumi YOKOYAMA