Abstract: A solid-state imaging device includes a plurality of pixels formed on a silicon substrate. Each pixel includes: a photoelectric conversion region formed in a surface portion of the silicon substrate; an uneven pattern including a recess and a protrusion, provided on a surface of the silicon substrate in the photoelectric conversion region; a first material film that covers a side surface of the uneven pattern, a bottom surface of the recess, and a top surface of the protrusion, while leaving a void in the recess; and a second material film that fills the void. The first material film has a refractive index higher than that of the second material film, and the refractive indices of the first material film and the second material film are both 1.7 or less.

Abstract: A powerless event monitor that includes a keeper device that includes a keeper floating gate, a keeper charging interface that is configured to charge the keeper floating gate before a beginning of a monitoring period, and a keeper discharge path that is triggered to discharge the keeper floating gate upon an occurrence of an event during the monitoring period. The powerless event monitor also includes a timer device that is coupled to the keeper device, that includes a timer floating gate, timer charging interface that is configured to charge the timer floating gate before the beginning of the monitoring period, and (c) a conditional timer floating gate discharge path that is configured to discharge the timer floating gate following at least a partial discharge of the keeper floating gate, wherein a charge of the timer floating gate during the discharging of the time floating gate is indicative of a time lapsed from the occurrence of the event.

Abstract: A photonic integrated circuit that consists essentially of: a first die; and a second die that is bonded to the first die; wherein the first die includes a first silicon layer and an additional layer, a modulating electrode and a silicon nitride waveguide formed in the additional layer; and wherein the second die includes a patterned structure made of at least one electro-optical modulation material that is selected of lithium niobate, lithium titanate, barium titanate or graphene; wherein the patterned structure includes: an input region that is configured to receive radiation; a modulating region in which the radiation is modulated under a control of the modulating electrode to provide modulated radiation, and an output region that is optically coupled to the silicon nitride waveguide for providing the modulated radiation to the silicon nitride waveguide.

Abstract: A photonic integrated circuit that consists essentially of at least one pair of a first die and a second die. For each pair the second die is bonded to the first die, the first die comprises an unpatterned electro-optical modulation layer that is positioned between a first silicon layer and a first buffering layer; wherein the unpatterned electro-optical modulation layer is made of at least one electro-optical modulation material that is selected of lithium niobate, lithium titanate or barium titanate; and the second die comprises (a) a thinned silicon substrate, (b) backside conductive paths that comprises contact pads accessible from one or more openings that are formed within the thinned silicon substrate, and (c) photonics elements that comprise (i) silicon nitride waveguides that are optically coupled to the unpatterned electro-optical modulation layer, and (ii) one or more photodetectors; wherein the at least one second die lacks a buried oxide layer.

Abstract: A photonic integrated circuit that consists essentially of: a first die; and a second die that is bonded to the first die; wherein the first die includes a first silicon layer and an additional layer, a modulating electrode and a silicon nitride waveguide formed in the additional layer; and wherein the second die includes a patterned structure made of at least one electro-optical modulation material that is selected of lithium niobate, lithium titanate, barium titanate or graphene; wherein the patterned structure includes: an input region that is configured to receive radiation; a modulating region in which the radiation is modulated under a control of the modulating electrode to provide modulated radiation, and an output region that is optically coupled to the silicon nitride waveguide for providing the modulated radiation to the silicon nitride waveguide.

Abstract: An apparatus may include a processor configured to process photodiode signal information, which corresponds to a plurality of photodiodes of an aerial vehicle, for example, to identify a plurality of electric currents, which may be generated by the plurality of photodiodes based on energy of a light beam to charge a battery of the aerial vehicle. The processor may be configured to determine a vehicle-position displacement to displace the aerial vehicle based on the plurality of electric currents. The vehicle-position displacement may be configured to adjust a photodiode-beam relative position of the plurality of photodiodes relative to the light beam. The apparatus may include an output to provide position displacement information based on the vehicle-position displacement.

Abstract: A semiconductor memory device includes a plurality of memory cells formed on a semiconductor substrate. Each of the memory cells includes a first floating gate transistor (TFG1), a second floating gate transistor (TFG2), a first erasing element, a second erasing element, and a memory cell selection transistor. A gate of TFG1 is electrically coupled to a gate of the first erasing element. A gate of TFG2 is electrically coupled to a gate of the second erasing element. A source of TFG1 is electrically coupled to a drain of the memory cell selection transistor. A source of TFG2 is electrically coupled to the drain of the memory cell selection transistor or a drain of TFG1.

Abstract: A semiconductor device includes a semiconductor substrate, an interlayer insulating film and an element region formed on the semiconductor substrate, and first and second seal rings surrounding the element region. Each of the first and second seal rings is formed of a layered conductive film including at least one linear interconnect layer and at least one linear via layer, and are insulated from each other or electrically connected only in an uppermost one of layers forming the conductive film. The first seal ring is electrically insulated from the semiconductor substrate. The second seal ring is electrically connected to the semiconductor substrate.

Abstract: A robust near infrared sensing device and method for operating of robust near infrared device, the method includes (i) exposing a first side edge of the device to near infrared (NIR) radiation; (ii) detecting by a NIR PIN diode (NPD), the NIR radiation, while operating at a fully depletion mode, (iii) collecting, by guard PIN diodes positioned at different sides of the NPD and while operating in the fully depletion mode, electron-hole pairs generated by unwanted radiation from any side of different sides of the near infrared PIN diode, and preventing these electron-hole pairs from any side of NPD to reach the NPD.

Abstract: For example, a sensor die may include a plurality of pixel sensors configured to sense ionizing radiation. The plurality of pixel sensors may include a plurality of detection diodes. For example, the plurality of detection diodes may be in a surface region of a silicon substrate of the sensor die. The plurality of detection diodes may be formed of a diode material. For example, the sensor die may include a plurality of dummy-diode diffusions in the surface region of the silicon substrate. The plurality of dummy-diode diffusions may be in a plurality of gettering regions between the plurality of detection diodes. The plurality of dummy-diode diffusions may include the diode material. For example, a width of the dummy-diode diffusion may be no more than 5 percent of a width of a detection diode of the two adjacent detection diodes.

Abstract: A radiation sensing device, that includes a sensing region that includes a radiation sensor, and an exterior region that includes a first guard element, a field limiting region, an array of surface holes and one or more sub-surface inner spaces. The exterior region is configured to prevent breakdown of the radiation sensing device at a presence of a surface charge created due to the radiation. The array of surface holes and the sub-surface inner spaces are located between the first guard element and the field limiting region and are configured to reduce the capacitance pf the exterior region.

Abstract: A NIR spectrometry device that includes different NIR PIN diodes (NPDs) and a guard PIN diode (VLPD) that are operated in a fully depletion mode. The different NPDs are located at different lateral positions corresponding to absorption depths of different NIR wavelengths. Each NPD is configured to collect electron-hole pairs (EHPs) generated by radiation that passes through a side edge of the device at a wavelength having an absorption depth that corresponds to a lateral position of the NPD. The VLPD is located at a lateral position that corresponds to a distance from the side edge that exceeds an absorption depth of visible light. The VLPD is configured to collect EHPs generated by unwanted radiation that passed through the side edge of the NIR spectrometry device and to prevent the EHPs generated by unwanted radiation to reach any of the different NPDs.

Abstract: For example, a radiation detector may include a bonded die including a plurality of active pixel sensors configured to sense ionizing radiation. For example, the bonded die may include a detection die including a plurality of detection diodes. For example, an active pixel sensor of the plurality of active pixel sensors may include a detection diode of the plurality of detection diodes to generate an electric detection signal based on detected ionized radiation detected by the detection diode. For example, the bonded die may include an electronic-circuitry die bonded to the detection die. For example, a thickness of the electronic-circuitry die may be less than 4 percent of a thickness of the detection die. For example, the electronic-circuitry die may include a plurality of transistors. For example, the active pixel sensor may include one or more transistors of the plurality of transistors to amplify the electronic detection signal.

Abstract: There is provided a method that includes (i) removing organic polymer residuals formed on a dry-etched hole that leads to a semiconductor structural element and coating the dry-etched hole with a non-organic polymer to provide a coated hole by exposing the dry-etched hole to a gaseous mixture, the gaseous mixture includes a fluorine based chemical compound, before the removing, the dry-etched hole was least partially coated with dry-etch residuals that comprise the organic polymer residuals; and (ii) coating the coated hole and removing fluorine based chemical compound residuals to provide an additionally coated hole by exposing the first coated hole to a nitrogen based plasma.

Abstract: A semiconductor device includes a memory cell on a semiconductor substrate. The memory cell includes a memory element, a first assistance element, and a second assistance element. The memory element includes a source region and a drain region, and a selection gate and a floating gate in series therebetween. The first assistance element includes a first impurity region and a first gate. The second assistance element includes a second impurity region and a second gate. The first and second gates are electrically connected to the floating gate. The second impurity region is connected to a signal line that is connected to the drain region or a signal line that is connected to the selection gate.

Abstract: A solid-state imaging device includes an N-type semiconductor layer, an element layer including a photoelectric conversion element and an active element, an interconnect layer providing an interconnect for the active element, and an element isolation trench penetrating the semiconductor layer. The element layer includes a P-type region and an N-type region. A first hole storage layer is formed on a surface of the semiconductor layer on a side opposite to the element layer. A second hole storage layer is formed in contact portions of the semiconductor layer and the element layer with the element isolation trench. The P-type region of the element layer and the first hole storage layer are connected to each other by the second hole storage layer.

Abstract: For example, an apparatus may include a processor configured to process photodiode signal information, which corresponds to a plurality of photodiodes of an aerial vehicle, for example, to identify a plurality of electric currents, which may be generated by the plurality of photodiodes based on energy of a light beam to charge a battery of the aerial vehicle. For example, the processor may be configured to determine a vehicle-position displacement to displace the aerial vehicle based on the plurality of electric currents. For example, the vehicle-position displacement may be configured to adjust a photodiode-beam relative position of the plurality of photodiodes relative to the light beam. For example, the apparatus may include an output to provide position displacement information based on the vehicle-position displacement.

Abstract: A method for manufacturing an optical system, the method includes obtaining an intermediate semiconductor item that comprises a silicon substrate and a stack of layers that comprises a monocrystalline silicon layer and is positioned between two silicon alloy layers; wherein the silicon substrate comprises diffusion regions; and performing Complementary Metal-Oxide-Semiconductor (CMOS) compliant operations to provide, based on the intermediate semiconductor item, a first switching cell that is formed on the silicon substrate.

Abstract: An optical switching system, including a silicon substrate; a first switching cell that is formed on the silicon substrate, wherein the first switching cell includes first till thirs ports, a monocrystalline silicon waveguide (MSW) that comprises a first MSW segment and a second MSW segment; and an actuation unit that is configured to move each one of the first MSW segment and the second MSW segment between at least three different positions thereby determining whether an optical signal received at the first port is (a) directed through the MSW to the second port, or (b) is directed to the third port through a first bus waveguide.

Abstract: For example, a multi voltage-domain Electro Static Discharge (ESD) power clamp may include a plurality of pins; and an ESD array including a cascaded plurality of ESD power clamps. For example, the ESD array may include a plurality of ESD array portions configured to protect a respective plurality of voltage domains from ESD. For example, the ESD array may be configured to connect the plurality of ESD array portions between a respective plurality of pin pairs from the plurality of pins. For example, an ESD array portion corresponding to a voltage domain may include one or more ESD power clamps of the cascaded plurality of ESD power clamps. For example, the ESD array portion may be configured to protect a voltage range of the voltage domain.