Abstract: Embodiments of noise reduction systems and methods are disclosed. One method embodiment, among others, comprises transforming a residual signal to produce transform coefficients, and applying the transform coefficients to a quantization matrix and a configurable gain matrix to provide a frequency-selective weighting of the transform coefficients having a gain that is sensitive to noise levels.

Abstract: A method of scanning lines in a display, a device for scanning lines and a portable electronic device including such a device scan lines consecutively for a set of scanning cycles and vary the selection of subfield from line to line in each scanning cycle such that subfields are selected in a consecutive order from line to line, no two consecutive line scans use the same subfield and no line is scanned using the same subfield twice during the set of scanning cycles.

Abstract: The invention relates to a method for rendering an image sequence. wherein an individual image is rendered by rendering monochromatic subimages in temporal succession. A subimage sequence obtained by temporal sequencing of the subimages is generated in motion-compensated fashion.

Abstract: A bit sequence (b, b?) from QPSK or QAM symbols is decoded, in which an associated receive probability (w, w?) is assigned to each receive bit (b, b?). The receive probability (w, w?) is adaptively determined taking into account the transfer properties of the channel.

Abstract: The invention relates to a method for determining the sampling instant of a clock signal (ti) for a circuit for determining symbols (Se) from a digitized signal (sd, S) which is coupled to at least one quadrature signal pair of a modulation method (QAM), wherein the digitized signal is converted to polar signal coordinates (R, ?) with a radial component (R).

Abstract: A method of controlling the operation of an equalizer (210, 216), wherein the equalizer is adapted to receive a transmitted signal (76, 78) comprising at least one predetermined sequence of symbols, includes the step of developing a set of samples from a received signal. At least one plurality of samples is identified, wherein the at least one plurality of samples corresponds to the at least one predetermined sequence of symbols. The equalizer is then operated in a selected one of three modes. A first mode is selected if the at least one plurality of samples is identified, wherein the first mode includes the step of developing a signal-to-noise ratio (SNR) (100). A second mode is selected if the at least one plurality of samples is identified and the SNR is greater than a first predetermined threshold. A third mode is selected if the at least one plurality of samples is identified and the SNR is greater than a second predetermined threshold.

Abstract: Method for motion-vector-aided interpolation of a pixel of an intermediate image lying between two input images includes a first pixel being selected from a first field and a second pixel being selected from a second field using a first motion vector, and a third pixel being selected from the first field and a fourth pixel being selected from the second field using a second motion vector. Next, an interval specified by video information values of the first pixel and the second pixel or an interval specified by video information values of the third pixel and the fourth pixel is determined and the video information values are mixed such that the video information value of the pixel to be interpolated lies within this interval.

Abstract: A Viterbi decoder includes a computing device, a memory and a bus. The computing device receives sets of data values and calculates distances for the received sets of data values, accumulates and compares the calculated distances according to a Viterbi algorithm, decides data values and generates control signals dependent on a plurality of decisions associated with a plurality of paths. The memory stores the decided data values and provides at least one output value. The bus connects the computing device and the memory and is configured to convey the control signals to the path memory. The computing device or the memory shifts data strings in the memory according to conditions of the Viterbi algorithm with the control signals associated with the plurality of paths.

Abstract: A baud rate acquisition circuit (10) for synchronizing a sampling signal with an input signal operates in broad rate sweeping and a rate fine tuning phases. In the rate sweeping phase, a timing error detector (24) examines the sampling signal generated by a decimator (16). If the sampling signal is outside a rate acquisition range from the target rate, a rate sweeping algorithm selects a new sampling rate. In response to the sampling rate within the rate acquisition range, the timing error detector (24) examines the asymmetry thereof to generate a rate correction signal to synchronize the sampling signal with the input signal. Next in the rate fine tuning phase, a multiplexer (22) routes the sampling signal through a square root filter (18). By examining the waveform shaped signal, the time error detector (24) synchronizes the sampling signal with the input signal with high accuracy.

Abstract: A method of controlling a feedforward filter of an equalizer includes the steps of generating a complex representation of an output of the feedforward filter and generating a representation of a decision from an output of the equalizer. The complex representation and the decision representation are correlated to obtain a phase error estimate. A phase correction value is generated based on the phase error estimate and used to adjust the phase of the output of the feedforward filter.

Abstract: The present invention provides a system and method for adjusting clock phase in a digital display. The display 10 may include a target analog-to-digital converter 104 that generates a first digital signal based on an analog input signal and a first clock signal (CLK1). The system 100 includes a first clock phase adjustment circuit 108, which provides CLK1 to the target analog-to-digital converter 104. A second analog-to-digital converter 106 receives at least a portion of the analog input signal and a second adjusted clock signal (CLK2), and generates a second digital signal based on these inputs. A second clock phase adjustment circuit 100 is communicatively coupled to the second analog-to-digital converter 106, and transmits CLK2 to the second analog-to-digital converter. A controller 112 receives the second digital signal from the second analog-to-digital converter 106 and uses the signal to determine a preferred phase of CLK2.

Abstract: Method and apparatus by which digital data is communicated from a computer system to a display device. An analog video signal received from a computer system includes a predetermined data pattern. The analog video signal is sampled to detect the predetermined data pattern. The digital data is then recovered from the detected predetermined data pattern. The predetermined data pattern may occur a predetermined time interval after a horizontal sync pulse or may occur outside of a blanking interval. The display device may respond to the predetermined data pattern by commencing a set-up process, such as, adjusting a sampling rate for sampling the analog video signal; adjusting a sampling phase; or adjusting an orientation of a display image for the display device. Adjusting an orientation may comprise adjusting a sampling start time relative to a horizontal or vertical sync pulse. The predetermined data pattern may be representative of a parameter of the analog video signal, such as, resolution or frequency.