Abstract: A method and system for designing a two-stage operational amplifier having low total harmonic distortion. The method begins with estimating a gain level of a second stage of the operational amplifier. Then a transconductance of the second stage is calculated. A unity gain frequency level for the first stage is calculated and from that the one kilohertz gain level of the first stage. The gain level at one kilohertz is then calculated and from this, the unity gain frequency for the operational amplifier is then calculated. A value of the compensation capacitor for said operational amplifier is calculated followed by calculating a transconductance of a first stage of the operational amplifier. The overall D.C. gain level and the output resistance of the first stage of the operational amplifier is then determined.

Abstract: A method and circuits are disclosed for an operational amplifier operating from a single cell 1.5 Volt supply which consumes very little power, and which can handle rail-to-rail input common mode and output signal swings. Low voltage and low power operation are made possible by biasing the CMOS transistors of the entire operational amplifier in the so called “sub-threshold” or “weak inversion” region of operation. This lowers VGSN and VGSP below VTN and VTP, and also lowers VDsat so that the operational amplifier can operate down to 0.9 Volt. The Class AB control circuit part of the operational amplifier can be applied to any conventional (normal biasing—other than weak inversion) low voltage Class AB output stage. The output stage of the operational amplifier is designed to source and sink more than 60 microAmperes of current into a 10 Kohm load while consuming only 4 micoramperes of current in the quiescent state.

Abstract: Disclosed is a fully differential switched-capacitor integrator which accepts a single-ended or unbalanced input signal and compensates the offset and finite gain of the operational amplifier without an extra converter circuit. The proposed circuit utilizes a special input structure which adds special capacitors to store the offset and the low frequency noise of the operational amplifier. One preferred embodiment implements the switching means as transmission gates using CMOS transistors. Clock feedthrough is prevented by providing two non-overlapping clock phases with a delayed clock each, thus avoiding clock feed-through. The invention provides a good alternative for applications such as low noise filters and sigma delta modulators.

Abstract: Methods and circuits are disclosed for low voltage (1.5 Volt and below) CMOS circuits, offering good transconductance and current driving capabilities. These goals are achieved by biasing CMOS transistors in the weak inversion region, by utilizing multiple unit-sized transistors with a fixed gate width to gate length ratio, and by maintaining a uniform threshold voltage of each unit-sized transistor. The required transistor size is obtained by parallel connection of several unit-sized transistors, such that `n` unit sized transistors carry the required current of `n` units. The methods and circuits disclosed eliminate deviation of the output current of current mirrors caused by threshold voltage mismatch. Disclosed are a current mirror and two typical amplifiers as examples of weak inversion design.

Abstract: In the present invention is described a forward feed sigma delta modulator of higher order having automatic saturation detection and recovery. The modulator is separated into two parts which are connected together when there is no saturation, and disconnected when saturation is detected and recovery takes place. The first part contains an integrator and input output circuitry to allow continuous operation of the modulator. The second part contains additional integrators to provider for a higher order modulator and the saturation detector. The modulator can be constructed of single ended or differential switched capacitor technology, and there is a digital saturation detection scheme.

Abstract: A stacked capacitor that has a large capacitance per unit area (Co), very low voltage coefficient (Kv), and an acceptable parasitic capacitance factor (Kp) is described that uses only one polysilicon layer. The stacked capacitor is formed at the surface of a semiconductor substrate of a first conductivity type. The stacked capacitor has a bottom plate that is formed by a lightly doped well diffused into the surface of the semiconductor substrate. The bottom plate also has a first plurality of interconnected conductive layers of a first conductive material disposed above and aligned with the well, whereby a first conductive layer of the first plurality of conductive layers is connected to the well by multiple contacts distributed over an area of the well.

Abstract: A circuit and a method are disclosed which offer a solution for integrating a power-on-reset circuit that is realizable in a small space, consumes very little power, and works for practically any rate of rise of the power supply. These goals have been achieved by detecting, in a first section of the circuit, when the supply voltage reaches the threshold voltage V.sub.TP of a p-channel transistor, and activates power-on-reset by forcing that signal to logical zero (active). This first section detects next when the supply voltage reaches 2V.sub.TP and signals to a second section of the circuit to start charging a capacitor. The charging rate of the capacitor is controlled in such a way that its voltage lags behind the supply voltage, so that if the rise of the supply voltage is very fast, the duration T.sub.D of power-on-reset is long enough to insure complete resetting of the circuits it serves, such as digital memory elements, digital registers etc.

Abstract: A single integrated-circuit color camera chip is color sensitive by grouping closely-adjoining light-detecting cells in a photodiode array into triplets. Each pixel of the sensor includes both a read transistor and a write transistor. Each cells in the triplet is similar, but each cell is associated with a color filter of a different color, with red, green or blue cells in an R-G-B system. The proximity and small size of the cells in a triplet allows accurate color differentiation each pixel. Color information is adjusted on-chip for color, brightness and contrast before being sent to an external read device or display device. The color filter is a series of passive layers formed on the integrated circuit surface permitting the selective transmission of light or electromagnetic radiation of certain frequency ranges. The filter may be coated onto a semiconductor wafer after the latter has undergone conventional MOS process steps.

Abstract: A variable high frequency voltage controlled oscillator (VCO) which is fully integrated. By controlling, with a control voltage, the collector current flowing through one transistor of the integrated oscillator circuit, the diffusion capacitance (also known as base-charging capacitance) of that transistor is varied. Since, in conjunction with an inductance, this capacitance to a large degree determines the frequency of oscillation of the integrated circuit, a fully integrated VCO is made possible.

Abstract: This invention is an electronic time constant tuning circuit that uses a frequency of a clock to tune the circuit time constant. A first transconductor is used to charge a capacitor to two different voltages, each for a separate portion of a clock period. A second transconductor is used to compare the two voltages and control them to be equal by controlling the transconductance of the first transconductor. When the two voltage are equal, the resulting transconductance and the capacitance of the capacitor form the circuit time constant. The circuit time constant can readily be changed by changing the frequency of the clock. The control signal generated by the second transconductor can be applied to other transconductors in a gm-C filter to adjust the cutoff frequency of the filter when the other transconductors have a similar structure to the first transconductor.

Abstract: A circuit and a method are disclosed for a power start-up reset circuit which is self-timing and which can be fully integrated in a standard CMOS or BiCMOS process along with other digital circuits. The circuit provides a system reset signal which is issued only after all circuit have stabilized by making the issuance of this system reset signal dependent on an oscillator becoming stable and a subsequent count of a fixed number of system clock cycles derived from that oscillator.

Abstract: In this invention a time constant tuning circuit is described in which a reference clock frequency is used to adjust the gm of a transconductor and as a result the time constant of the circuit. This is done by charging a capacitor to a voltage with the current output of a transconductor during a clock period and comparing the voltage charge with another voltage. The error voltage from the comparison is used to control the gm of the transconductor. Changing the clock period changes the gm required to charge the capacitor to a voltage to satisfy the comparison. Thus the filter time constants are directly proportional to the reference clock; and therefore, are independent of process variations. The time constants can be varied by varying the clock frequency and is achieved without the use of a PLL. The output the time constant tuning circuit can be used to tune the time constants of other gm-c filters using similar transconductors and capacitors.

Abstract: A multiple frequency shifting oscillator that will provide a plurality of frequencies dependent upon a contents of an input shifting signal an input shifting signal is disclosed. The multiple frequency shifting oscillator has an amplifier with first input, a second input, which is coupled to a ground reference potential and an output. The multiple frequency shifting oscillator has a first impedance that is coupled between the first input of the amplifier and the ground reference potential, a second impedance that is coupled between the output of the amplifier and the ground reference potential, and a third impedance coupled between the output and the input of the amplifier. The multiple frequency shifting oscillator has a plurality of frequency shifting impedances that when selected will be coupled to the first impedance so as to shift the frequency of the multiple frequency shifting oscillator.

Abstract: A multilevel capacitor structure compatible with CMOS processing for use in switched capacitor circuits is disclosed. The capacitor structure has an associated parasitic capacitor which is placed in such a way so as to minimize the impact on the performance of a the switched capacitor circuit. The parasitic capacitor is formed between a first plate of the shielded capacitor and a diffusion well within a substrate. The diffusion well is connected to a quiet voltage reference source to isolate the shielded capacitor from noise present on the substrate. The shielded capacitor has a first plate that is fabricated from a first conductive material such as polycrystalline silicon or polycide, a second plate fabricated from a second conductive material such as a first level of metal on an integrated circuit, and a third capacitor plate fabricated from a second level of metal of an integrated circuit.

Abstract: A resistor network having a precise ratio of resistances of all resistors within the network while having a compact layout to minimize area is described. The integrated circuit resistor network has a plurality of unit resistors. Each unit resistor is composed of a thin film resistive material. The area of the thin film resistive material to form the unit resistor is a median value of the resistor elements to be formed into said integrated circuit resistor network. Each unit resistor has a contact means to connect to the plurality of unit resistors. A plurality of metal interconnection segments will connect to the contact means to form said integrated circuit resistor network. A plurality of metal conductive segments are connected to a metal interconnection segments and to external circuitry to connect the external circuitry to the integrated circuit resistor network.

Abstract: A fractional period delay circuit to delay a clocking signal by a non-integer fraction of the period of the clocking signal is disclosed. The fractional period delay circuit has a first delay line connected to a master timing signal to delay the master clock to form the first timing signal. The fractional period delay circuit has plurality of adjustable delay lines. Each adjustable delay line is connected to the master timing signal to delay the master timing A delay adjustment input will modify the delay of the adjustable delay circuit. The fractional period delay circuit further has a plurality of phase difference detectors connected to the output of the first delay line and to the output of one of the plurality of adjustable delay lines. The phase difference detector will create a difference signal indicating a difference in phase between the first timing signal and one of the delayed timing signals. A plurality of sequence timing signals are created in a is timing sequence generator.

Abstract: A pseudo random pulse generator that creates a series of pulses having randomly separated intervals is described. A pseudo random pulse generator has a pseudo random number generator create a series of pseudo random binary numbers. An enable input initiates creating the series of pseudo random binary numbers and a clock input is connected to a clock signal that synchronizes creating the series of pseudo random binary numbers. A hold input prevents the generation of the pseudo random binary numbers. The pseudo random pulse generator has an interval selector to select one of a plurality of timing signals. Each timing signal is a power of two frequency division of the clock. The interval selector has select signal terminals to select one of the plurality of timing signals, and a trigger output to hold a selected timing signal. The pseudo random pulse generator further has a select buffer connected to a low order digits of the pseudo random number generator.

Abstract: A circuit and a method are disclosed to provide a tristate input/output buffer which is compatible with 5 volt input signals, applied to its output node, while operating with a 3 volt power supply. This is achieved by inserting an extra p-channel transistor in series with the existing p-channel transistor. The extra p-channel transistor and its parasitic diode are wired so that they will not conduct, i.e. the extra transistor is off and the parasitic diode is back-biased, when a 5 volt input signal is applied to the output of the tristate input/output buffer. Two additional transistors are used to control the on/off state of the extra p-channel transistor.

Abstract: A clock waveform synthesizer that will create a timing signal that is a multiple of the frequency of an master clock is disclosed and has the capability to programmably adjust the rising edges and falling edges of the synthesized waveform within the period of the master clocks. The clock waveform synthesizer has a multi-tapped delay line. The multi-tapped delay line will create replications of the master clock that are incrementally delayed from the master clock to create a plurality of delay signals. A fraction of the plurality of delay signals will be the inputs to each of a plurality of multiplexers. A select port on each of the multiplexers will receive a select signal to choose one delay signal of the fraction of the plurality of delay signals. The one selected delay signals will be the input to the set terminals and reset terminals of a plurality of edge-triggered set/reset flip-flops.

Abstract: A pitch synchronous sinusoidal synthesizer for multi-band excitation vocoders will produce excitation signals necessary to artificially mimic speech from input data. The input data will contain the pitch frequencies for current and previous synthesizing frame samples, starting phase information for all harmonics within the current synthesizing frame sample, magnitudes for each of the harmonics present within the current synthesizing frame sample, the voiced/unvoiced decisions for each of the harmonics within the current frame sample, and an energy description for the harmonics of the current synthesizing frame sample. The pitch synchronous sinusoidal synthesizer will produce the synthetic speech with a minimum of the distortion caused by the sampling and regeneration of the speech excitation signals. The pitch synchronized sinusoidal synthesizer has a plurality of pitch interpolators.