Abstract: A fractional period delay circuit to delay a clocking signal by a non-integer fraction of the period of the clocking signal is disclosed. The fractional period delay circuit has a first delay line connected to a master timing signal to delay the master clock to form the first timing signal. The fractional period delay circuit has plurality of adjustable delay lines. Each adjustable delay line is connected to the master timing signal to delay the master timing A delay adjustment input will modify the delay of the adjustable delay circuit. The fractional period delay circuit further has a plurality of phase difference detectors connected to the output of the first delay line and to the output of one of the plurality of adjustable delay lines. The phase difference detector will create a difference signal indicating a difference in phase between the first timing signal and one of the delayed timing signals. A plurality of sequence timing signals are created in a is timing sequence generator.

Abstract: A pseudo random pulse generator that creates a series of pulses having randomly separated intervals is described. A pseudo random pulse generator has a pseudo random number generator create a series of pseudo random binary numbers. An enable input initiates creating the series of pseudo random binary numbers and a clock input is connected to a clock signal that synchronizes creating the series of pseudo random binary numbers. A hold input prevents the generation of the pseudo random binary numbers. The pseudo random pulse generator has an interval selector to select one of a plurality of timing signals. Each timing signal is a power of two frequency division of the clock. The interval selector has select signal terminals to select one of the plurality of timing signals, and a trigger output to hold a selected timing signal. The pseudo random pulse generator further has a select buffer connected to a low order digits of the pseudo random number generator.

Abstract: A circuit and a method are disclosed to provide a tristate input/output buffer which is compatible with 5 volt input signals, applied to its output node, while operating with a 3 volt power supply. This is achieved by inserting an extra p-channel transistor in series with the existing p-channel transistor. The extra p-channel transistor and its parasitic diode are wired so that they will not conduct, i.e. the extra transistor is off and the parasitic diode is back-biased, when a 5 volt input signal is applied to the output of the tristate input/output buffer. Two additional transistors are used to control the on/off state of the extra p-channel transistor.

Abstract: A clock waveform synthesizer that will create a timing signal that is a multiple of the frequency of an master clock is disclosed and has the capability to programmably adjust the rising edges and falling edges of the synthesized waveform within the period of the master clocks. The clock waveform synthesizer has a multi-tapped delay line. The multi-tapped delay line will create replications of the master clock that are incrementally delayed from the master clock to create a plurality of delay signals. A fraction of the plurality of delay signals will be the inputs to each of a plurality of multiplexers. A select port on each of the multiplexers will receive a select signal to choose one delay signal of the fraction of the plurality of delay signals. The one selected delay signals will be the input to the set terminals and reset terminals of a plurality of edge-triggered set/reset flip-flops.

Abstract: A pitch synchronous sinusoidal synthesizer for multi-band excitation vocoders will produce excitation signals necessary to artificially mimic speech from input data. The input data will contain the pitch frequencies for current and previous synthesizing frame samples, starting phase information for all harmonics within the current synthesizing frame sample, magnitudes for each of the harmonics present within the current synthesizing frame sample, the voiced/unvoiced decisions for each of the harmonics within the current frame sample, and an energy description for the harmonics of the current synthesizing frame sample. The pitch synchronous sinusoidal synthesizer will produce the synthetic speech with a minimum of the distortion caused by the sampling and regeneration of the speech excitation signals. The pitch synchronized sinusoidal synthesizer has a plurality of pitch interpolators.

Abstract: This invention describes a circuit and method for creating a double clock frequency. The circuit uses a sequence of delay elements to delay the primary clock. A delay detector determines when a delayed clock is out of phase with the primary clock. A delay is selected that is one half the delay producing the out of phase delayed clock. The selected delay is used to combine with the primary clock to produce a double clock frequency. Control signals for selecting the "half" delayed clock are latched to prevent clock jitter and spurious signal from producing error signals in the double frequency clock. Different duty cycles can be established by varying the selected delay.

Abstract: Systems and methods for the detection of motions of a pointed object upon a writing surface such as a touchpad is disclosed. The motions will be detected and converted in a multiplexing analog-to-digital converter to digital codes representing the location of the pointed object and the pressure of the pointed object upon the touchpad. The location and the pressure will be translated into a pen detect signal indicating the presence of the pointed object upon the touchpad. The pen detect signal will be translated into a stroke signal to interpret a single tap, a double tap, and a tap and drag of the pointed object on the touchpad. The digital codes will be averaged to minimize noise and formed into an absolute coordinates digital code. The absolute coordinate digital code, the pressure digital code, and the pen detect signal will be converted to a touchpad-computer interface protocol. Further, multiple sets absolute coordinates will translated into a relative motion code.

Abstract: This invention describes a numeric intensive development environment for producing code for various fixed point DSP's and providing a debug capability that assists the user by displaying various data from the DSP in various formats. The DSP code is created in a DSP-C language which is based on low level assembly language tools enhanced with extensive native mathematical representation formats and high level language syntax. This provides the advantage of handling numeric representation in high level language and optimizing the code for speed and compactness in low level language. Once the code is created in DSP-C it can be connected to a DSP through a driver and driver interface. The driver interface allows the code to be universal with a different driver being used to connect the code to different DSP's. In debug mode data from a target DSP is continuously fetched allowing the user to make real time modifications to the code and get real time feed back of the results.

Abstract: A method and means to estimate the pitch of a speech or acoustic signal within a vocoder begins with the center clipping and low-pass filtering of the speech or acoustic signal to eliminate the formants from the speech or acoustic signal. An error function for each pitch is calculated for each pitch within the speech or acoustic signal. A fast tracking method is used to select the estimated pitch for the pitch or acoustic signal. A final check for the doubling of the pitch will minimize any incorrect estimation of the pitch.

Abstract: This invention describes a DAC requiring a substantially lower number of resistors for conversion of n+p digital bits. The conversion to an analog signal is done in two voltage dividers. The first voltage divider contains 2.sup.n resistors and is referenced to a voltage bias. The second voltage divider contains 2.sup.p resistors and is referenced to a current bias. The current bias is derived from a current mirror which references the current in the first voltage divider. The use of the current mirror allows all resistors in the DAC to be of the same value which in turn provides an implementation with better accuracy and resistor matching. The number of resistors required to make a conversion of a 12 bit digital signal is 272 where 8 bits are converted in the first voltage divider and 4 bits are converted in the second voltage divider.

Abstract: A circuit is disclosed for a complimentary metal oxide semiconductor (CMOS) operational amplifier output stage which can be connected easily to almost any input stage design and which can be coupled directly to that input stage. The circuit uses nine small transistors and two output transistors. The output transistors are connected in series between the power supply rails and the size of the two output transistors determines the current available to the load. The circuit of the invention can provide rail-to-rail output voltage swings and can drive a low ohm resistive load.

Abstract: An integrated circuit functions as an image detector providing an output signal representing the detected image. A two dimensional array of sensor cells is formed in rows and columns. A digital timing control means has outputs for providing timing signals. An address encoder is coupled to receive timing control signals from the digital timing control means. Each sensor cell has a photodiode and a first transistor having a first gate and having a source/drain circuit for precharging the cell and a second transistor having a second gate and a source/drain circuit for reading from the photodiode. The sensor cells are adapted for sensing electromagnetic radiation incident thereon. A plurality of sensor data amplifiers receives data from the cells. Means is provided for reading data from the cells into the sensor data amplifiers, and the sense amplifiers include an output circuit.

Abstract: To accomplish the above objectives, the present invention provides a method of fabricating a collector well in a semiconductor BiCMOS device. The method begins by providing a substrate having c-well areas, N-well areas, and P-well areas. The substrate has n-plug doped regions in said c-well areas. A stress release oxide layer is grown over the substrate surface. A first nitride layer 27 is formed over the stress release oxide layer 26. A C-well mask 29having C-well mask openings 28A is formed over C-well areas 28 and openings are formed in the first nitride layer. Impurities are implanted through the opening forming collector-well regions. The c-well mask is then removed. A n-well photoresist mask having n-well mask openings 42A is formed over the first nitride layer and openings are etched in the first nitride layer over N-well areas 40. Ions impurities are implanted through the n-well nitride opening 42A forming n-well regions 44 in the n-well area in the substrate 10. The n-well mask 42 is then removed.