Abstract: Systems and methods for the detection of motions of a pointed object upon a writing surface such as a touchpad is disclosed. The motions will be detected and converted in a multiplexing analog-to-digital converter to digital codes representing the location of the pointed object and the pressure of the pointed object upon the touchpad. The location and the pressure will be translated into a pen detect signal indicating the presence of the pointed object upon the touchpad. The digital codes will be averaged to minimize noise created by vibrations and variations in the motions of the pointed object held by the human hand and formed into an absolute coordinate digital code. The absolute coordinate digital code, the pressure digital code, and the pen detect signal will be converted to a touchpad-computer interface protocol for transmission to a computer system for further processing.

Abstract: A method and means for the control of a cursor upon a display screen of a computer system by a pointed object such as a pen, stylus, or finger upon an electrical writing surface is disclosed. The method and means will allow the cursor to continue to scroll across the display screen in a fixed direction and at a fixed speed once the pointed object has transited from a workzone region to an edgezone region of the touchpad. Once the pointed object is in the edgezone region, the pointed object may be stopped. If a different direction or speed of movement of the cursor is desired, the pointed object can be moved in the new direction to establish the new direction and speed of movement of the cursor. The control of the cursor will return to the normal movement when the pointed object returns to the workzone from the edgezone.

Abstract: The present invention provides a voltage controlled oscillator with improved noise immunity and minimized variation due to manufacturing process, power supply and operating temperature changes. The voltage controlled oscillator consists of fully differential connected ring oscillator that includes a plurality of differentially connected delay elements. The ring oscillator responds to a control current signal for controlling the frequency of oscillation. A voltage to current converter converts the input tuning voltage to an output current for the controlling of the ring oscillator. The delay element consists of two source coupled P-channel transistors connected to a current source. The drains of the P-channel transistors are each connected to a voltage controlled impedance that changes the delay characteristics of the delay element in response to the input tuning voltage.

Abstract: A cascoded differential amplifier with a circuit for the injection of current to enhance the gain is described. The differential amplifier includes a differential pair of n-MOS FET's connected to a current source an a positive and a negative input terminal. A pair of isolation n-MOS FET's are inserted between the differential pair and a pair of current source loads. These isolate the current source loads from the differential pair. A current injector is connected to the drains of the n-MOS FET's of the differential pair. The isolation n-MOS FET's and the injected currents enhance the gain of the differential amplifier. A level translation circuit adjusts the output levels of the differential pair to levels required by circuitry attached to the output terminals of the level translation circuitry.

Abstract: A multiply/accumulate computation circuit is provided. The circuit will perform the multiplication of a first binary number that is a multiplicand and a second binary number that is a multiplier to produce a product. The product can be added or subtracted from a previous result. The product may be negated. The product may be multiplied by a factor of two. Or the product that is multiplied by the factor of two may be added or subtracted from the previous result. The multiplication is accomplished in a modified Radix 4 Booth's encoding and translation circuit to produce a set of partial products that are combined in a n operand adder to form a final result.

Abstract: A novel ring shaped emitter structure with an extrinsic base and base contact in the central portion of the ring is described. This structural configuration is useful for improving the performance of bipolar transistors used in BiCMOS integrated circuits with only minimal changes to conventional CMOS processing technology. A single additional mask is required to form the intrinsic base region of the transistor. The emitter is diffused from a polysilicon layer which also serves as the emitter contact. The polysilicon layer overlies a perimeter portion of an active region defined by an opening in a field oxide and rises up over the field oxide itself. The active emitter region then forms a ring along the perimeter of the active region. The extrinsic base is formed through an opening within the polysilicon layer representing a central portion of the active region.

Abstract: An integrated circuit functions as an image detector providing an output signal representing the detected image. A two dimensional array of sensor cells is formed in rows and columns. A digital timing control means has outputs for providing timing signals. An address encoder is coupled to receive timing control signals from the digital timing control means. Each sensor cell has a photodiode and a first transistor having a first gate and having a source/drain circuit for precharging the cell and a second transistor having a second gate and a source/drain circuit for reading from the photodiode. The sensor cells are adapted for sensing electromagnetic radiation incident thereon. A plurality of sensor data amplifiers receives data from the cells. Means is provided for reading data from the cells into the sensor data amplifiers, and the sense amplifiers include an output circuit.

Abstract: To accomplish the above objectives, the present invention provides a method of fabricating a collector well in a semiconductor BiCMOS device. The method begins by providing a substrate having c-well areas, N-well areas, and P-well areas. The substrate has n-plug doped regions in said c-well areas. A stress release oxide layer is grown over the substrate surface. A first nitride layer 27 is formed over the stress release oxide layer 26. A C-well mask 29having C-well mask openings 28A is formed over C-well areas 28 and openings are formed in the first nitride layer. Impurities are implanted through the opening forming collector-well regions. The c-well mask is then removed. A n-well photoresist mask having n-well mask openings 42A is formed over the first nitride layer and openings are etched in the first nitride layer over N-well areas 40. Ions impurities are implanted through the n-well nitride opening 42A forming n-well regions 44 in the n-well area in the substrate 10. The n-well mask 42 is then removed.

Abstract: A system to transfer a serial digital data protocol between a controlling processor such as digital signal processor and a plurality of analog front-end devices is described. The system has a serial clock unit to generate a serial clock reference signal, a serial data control unit to create the serial data protocol, a serial clock transmission medium, a serial data transmission medium, and an analog front-end control unit. The serial digital data protocol has a start bit time, an address time, a read/write bit time, a first high impedance time, a serial data word time, a second high impedance time, and a stop bit time. A serial data word may be transferred either from the controlling processor to the analog front-end device or from the analog front-end device to the controlling processor dependent on the state at the read write bit time.

Abstract: A multiplexed analog-to-digital converter to accept multiple dissimilar analog input signals and convert each analog input signal to a digital code that represents the ratio of the magnitude of the analog input signal to the difference of an upper reference voltage source and a lower reference voltage source is disclosed. The upper reference voltage source is selected by an analog multiplexer from a set of voltage reference sources that include the power supply voltage source of the analog-to-digital converter for analog input signals that are reference to the power supply voltage source, and a precision reference voltage source that is referenced to the band-gap of silicon to provide an absolute measurement of the analog input signal. The lower reference voltage source is selected by a multiplexer from such references as a ground reference source.

Abstract: An operational amplifier with MOSFET's configured as capacitors provide frequency compensation over a large range of input frequencies is described. The operational amplifier has an differential amplifier stage with an inverting and an noninverting input. The difference of signals placed at the inverting and the noninverting inputs are amplified and place at the input of a folded cascode amplifier stage. The output of the folded cascode amplifier stage is the input to a linear amplifier stage. The output of the linear amplifier stage is connected to external loading circuitry. A first frequency compensation capacitor is connected between the output of the linear amplifier stage and a noninverted input of the folded cascode amplifier. A second frequency compensation capacitor is connected between the output of the linear amplifier stage and a virtual ground within the folded cascode amplifier stage.

Abstract: The linearity of a digital to analog converter is greatly enhanced by applying the same current to each of the nodes of a R-2R ladder network. This is accomplished by breaking the conversion cycle into n time slots and sequencing the connection of the current sources such that each will be connected to a different node in each of the time slots. In this way all the current sources will be connected to each node once in the conversion cycle and the current flowing into the each node will be the average value of all of the currents. Since each node receives this same average current, the linearity of the digital to analog converter is enhanced and is not a function of the mismatch of the applied current sources.

Abstract: An architecture and system for the implementation of an all digital frequency synthesizing system is described. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic input reference frequency counter. The periodic input reference frequency counter will count a number of periods of a periodic input reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output frequency will be toggled from logic level to another logic level. A new periodic output frequency period can be chosen by selecting a new series of count integers in the count retention table. This architecture is structured such that it can be implemented in an automated logic design system.

Abstract: A digital to analog converter (DAC) is shown which converts a floating point digital signal into an analog output. This is accomplishing by using one R-2R ladder network having more nodes than there are current generators to be connected to the nodes. The current generators representing the mantissa part of the digital signal are connected to the nodes of the single ladder network in a contiguous block arrangement and in order from the LSB to the MSB of the mantissa. The position of the block of current generators is controlled by the exponent part resulting in the proper scaling of the mantissa value in the output analog signal. Thus using fewer parts that must be accurately matched to provide a consistent accuracy and resolution over a wide range of input signal.

Abstract: A circuit for turning off an indicator light operates in two phases that provide a first rapid discharge phase and a second slow discharge phase. This sequence dims the light in a visual approximation of the exponential dimming that occurs with lights that operate with power supplies that have capacitors that give a slow turn off. The preferred light is an electroluminescent element that will be called a glow-effect capacitor which stores sufficient charge for slow turn off. When a switch associated with the light is opened, an FET turns on to discharge the capacitor rapidly to a selected voltage. This FET is then turned off and other components discharge the capacitor slowly. The switching signal for this FET is formed as a logic function of the switch position (open or closed) and the occurrence of the selected voltage level on the glow-effect capacitor.

Abstract: A tablet system has an improved operation for saving power. During a digitizing period, the tablet supplies power to resistive sheets that produce analog pen position signals and to the sample and hold circuit and the analog to digital converter that operate on these signals. During a wait state, power is removed from these components and a separate circuit detects contact with the tablet surface by a pen. A pen activity circuit that uses less power is also disclosed. The pen activity detecting circuit has a resistor in circuit with the two resistive sheets. This resistor and associated circuits are independent of the normal path for signals that denote pen position and thereby allow these components to be turned off. When the pen is positioned on the tablet surface, the two resistive sheets are brought into contact in the normal way for detecting the pen position. During a period of pen inactivity, this contact produces a current in the resistor.

Abstract: A digital tablet of the type that multiplexes pen position signals has filtering and digitizing circuits arranged in separate channels for each of the signals that is to be multiplexed. The tablet pen is connected to receive an oscillator signal and the signal is picked up at each of the four corners of the tablet and applied to the corresponding channel. The separate channels permit the filters to be made sharper. The disclosure also includes improved circuits for processing the pen position signals.

Abstract: A new controller transfers data directly between the register of an I/O port and an ALU register in an operation that takes only one phase of a two-phase clock cycle. A transfer between an ALU register and main memory is also performed in one phase, and the entire transfer can be accomplished in one clock cycle. A connection is also provided between the ALU registers and the flag register, and when the incoming byte is a status byte, the controller can transfer the byte to the flag register where it can control the next instruction execution.

Abstract: In a digital to analog converter of the type having an array of current sources that are selected according to a digital input code to produce a current sum that is an analog of the digital code, current sources are arranged in pairs to form a dual current cell. When a dual current cell is selected, it produces two currents of differing magnitudes that are summed on two output busses with corresponding currents from other selected dual cells. These currents are subtracted to form an analog current. The two currents tend to have similar errors from a nominal current value and these errors are canceled by the subtraction. The two current sources of each dual current cell are oppositely switchable between two current levels, and the number of current sources is the minimum number commonly used for arrays of current cells having only one current source.