Abstract: High efficiency DC to RF conversion with use of active harmonic insertion is provided for power amplification over a wide dynamic range of input signal level. Specifically, a power amplifier device including at least a final amplification stage is operated to receive an input signal of a fundamental frequency. A drive signal is produced which includes a fundamental signal component of the fundamental frequency and at least one harmonic signal component of a harmonic frequency that is substantially an integer multiple of the fundamental frequency, wherein relative phase shift and relative amplitude of the components are controlled over at least an order of magnitude of dynamic range of the input signal. As the signal level of the input signal decreases (or increases), the desired proportion of signal levels is maintained between the components.

Abstract: In a digital IF downconversion circuit, in-phase and quadrature signal components are processed in the form of a single serial digital bit stream through a set of simple logic in combination with a reconstruction filter. A source digital oscillator supplying digital signal mixers employs an oversampled digital word of four bits in length, all of which are binary weighted, to achieve at least sixteen levels of accuracy for a sine wave mixing signal without significant phase or amplitude error. The mixer mixes the digitized serial bit stream according to the clock with output of a four-bit wide table representing the source oscillator and the in-phase and quadrature signals are recombined digitally, followed by binary weighting using weighted resistors coupled into a filter. Thus, image rejection is a digital function which is unaffected by resistor tolerance.

Abstract: A communication filter circuit useful in a dual-mode receiver comprises a cascade of an active twin-T filter and a passive twin-T filter sections defining sharp notches at the center of second adjacent and of third adjacent channels, respectively, and specifically providing most attenuation at 60 kHz and at 90 kHz, for operation in the ISM136 band which has 30 kHz channel spacing. Since communication is channelized and limited in bandwidth, an active/passive twin-T notch filter structure is effective for signal attenuation. In a circuit in which real and imaginary signal components are processed, active-passive twin-T filters are provided in each of four signal paths, namely I and −I, Q and −Q.

Abstract: In a portable dual mode receiver circuit, a dual modulus clock system is provided which can, by selective use of integer division on a multiplied master clock, select specific channels with two different channel spacings in several different bands, providing power and space savings and achieving simplicity of operation.

Abstract: An apparatus and method are provided for attenuating an undesired frequency (f1) relative to a desired frequency (f0) in a signal transmitted from an out-put (220) of an active element (210). Generally, the apparatus includes a parallel-resonant trap (145) coupled to the output of the active element (210), the trap including a network of reactive elements (235).

Abstract: The present invention, generally speaking, provides for bandwidth switching of a PLL in a simple, effective manner. In accordance with one embodiment, a phase lock loop includes a controlled oscillator responsive to a control voltage for producing an output signal of some output frequency; a comparator responsive to a feedback signal derived from the output signal and to a reference signal for producing at least one error signal; a charge pump circuit including multiple pairs of unidirectional current sources (or, alternatively, multiple bidirectional current sources); a control circuit responsive to a control signal for activating one or more pairs of unidirectional current sources, at the same time deactivating one or more pairs of unidirectional current sources; and a loop filter responsive to the multiple pairs of unidirectional current sources for producing the control voltage governing the output frequency.

Abstract: The present invention, generally speaking, achieves a highly efficient line driver for high crest-factor signals such as DMT/ADSL signals. In an exemplary embodiment, a digital signal produced by a digital signal processor or the like is processed by a sigma-delta modulator to produce one or more binary signal pairs. The signals of a signal pair are low-pass filtered, if necessary, and applied across the winding of a transformer. The transformer has a single secondary winding connected to the line and may has as many primary windings as the number of signal pairs. The transformer may have a unity turns ratio or may have a turns ratio for accomplishing voltage step-up. For one signal pair, the number of possible resulting signals levels on the secondary side is three, for two signal pairs five, etc. Using more than two signal levels, it becomes possible to recreate from the digital signals the corresponding analog waveform with the required accuracy.

Abstract: The present invention, generally speaking, provides methods and apparatus for avoiding saturation of a transistor, with particular application to communications signal amplifiers. In accordance with one aspect of the invention, feedback circuitry is provided to control a transistor in accordance with a control signal. The combination of current monitor and a threshold comparator detects when the base current of the transistor exceeds a threshold, indicative of the onset of saturation. Feedback control is then modified to prevent saturation.

Abstract: The present invention, generally speaking, provides a circuit that combines the features of a voltage doubler and a boost regulator to achieve a small and efficient voltage boost regulator. A capacitor is used to provide a primary voltage boost effect. An inductor is used to provide further regulation, either further boost or buck. Instead of requiring non-overlapping clock signals, the relative timing and overlap of the clock signals determines the regulation achieved. The inductor can be made significantly smaller than in comparable boost circuits, facilitating size reduction.

Abstract: The present invention, generally speaking, allows for a substantial reduction in oscillator phase noise by modifying the transfer function of a portion of the oscillator, e.g., by adding a zero to the transfer function. Modifying the transfer function reduces the open-loop gain of the oscillator but achieves a desired phase compensation, allowing the oscillator to be operated at the resonance of the resonator instead of off resonance. In an exemplary embodiment, the transfer function is modified by choosing a capacitance value such that, instead of operating as a bypass at the frequency of interest, adds a zero to the transfer function of the oscillator and causes a change in frequency characteristics, achieving an increase in the effective Q of the oscillator. This increase in effective Q translates directly into reduced phase noise. Phase noise improvement in the range of 3dB has been demonstrated.

Abstract: The present invention, generally speaking, provides for high-efficiency power control of a high-efficiency (e.g., hard-limiting or switch-mode) power amplifier in such a manner as to achieve a desired modulation. In one embodiment, the spread between a maximum frequency of the desired modulation and the operating frequency of a switch-mode DC-DC converter is reduced by following the switch-mode converter with an active linear regulator. The linear regulator is designed so as to control the operating voltage of the power amplifier with sufficient bandwidth to faithfully reproduce the desired amplitude modulation waveform. The linear regulator is further designed to reject variations on its input voltage even while the output voltage is changed in response to an applied control signal. This rejection will occur even though the variations on the input voltage are of commensurate or even lower frequency than that of the controlled output variation.

Abstract: The present invention, generally speaking, incorporates the power amplifier as a fundamental constituent of a modulator, using polar modulation techniques. Thus, it is possible to achieve the combination of precision signal generation (including envelope variations) along with high energy efficiency in combinations not possible heretofore. In accordance with one embodiment of the invention, a modulated radio (passband) signal generator produces high quality signals of general type, which specifically includes signals with varying envelopes. Signals are generated with high energy efficiency in the conversion of applied DC power to output RF signal power. The result is longer battery life for products such as mobile phone handsets. Dramatically improved efficiency also allows for a dramatic reduction (10 to 1 or greater) in the size of any required heatsink for the radio transmitter, which significantly lowers both cost and size.

Abstract: An amplifier circuit formed on a single semiconductor substrate includes a first amplifier having at least one stage for amplifying signals within a first frequency band; a first amplifier having at least one stage for amplifying signals within a second frequency band; and a tapped coil having one end thereof coupled to a stage of the first amplifier and a tap thereof coupled to a stage of the second amplifier. The amplifier circuit may be an RF amplifier circuit, a first portion of the tapped coil serving as an RF choke for said stage of the first amplifier, and a second portion of the tapped coil serving as an RF choke for said stage of the second amplifier. Sharing the tapped coil between multiple band amplifiers increases integration density.

Abstract: The present invention, generally speaking, provides a simple, all-digital method and apparatus for determining the phase of a first clock signal relative to a second clock signal. The first clock signal may be a digital approximation of a periodic analog signal such as an RF signal. A sampling technique is employed that produces a stream of digital bits containing relative phase information. From the stream of digital bits is formed a digital word indicative of the relative phase. The digital word may be formed using a digital filter. Advantageously, an extensive body of digital filtering techniques applicable to Sigma-Delta (sometimes referred to as Delta-Sigma) A/D converters may be applied directly to the digital stream. By using an appropriately-chosen weighting function, high accuracy may be obtained.

Abstract: The present invention, generally speaking, provides a very simple, all-digital method and apparatus for determining the ratio of frequencies of two signals. One of the signal may be a known reference frequency, allowing the instantaneous frequency of an unknown input signal to be readily determined. A frequency sampling technique is employed that produces a stream of digital bits which contains information regarding the ratio of frequencies. From the stream of digital bits is formed a digital word indicative of the ratio of frequencies. The digital word may be formed using a digital filter. Advantageously, an extensive body of digital filtering techniques applicable to Sigma-Delta (sometimes referred to as Delta-Sigma) A/D converters may be applied directly to the digital stream. By using an appropriately-chosen weighting function, high accuracy may be obtained.

Abstract: The present invention, generally speaking, provides an improved power amplifier that minimizes impedance changes as the power amplifier changes from one operational state to another. In an exemplary embodiment, the present power amplifier is based on the well-known cascode amplifier. In a cascode amplifier, a first transistor operates in the common-source (common emitter) configuration to convert the input signal voltage (or current) into an amplified current, and a second transistor operates in the common-gate (common-base) configuration to convert the output current from the first transistor into an output voltage.

Abstract: The present invention, generally speaking, provides an RF amplifier circuit architecture that enables high efficiency to be achieved while avoiding complicated matching networks and load networks. The active device may be of the bipolar transistor type or the FET (field effect transistor) type. A simple driving circuit is provided for each type of active device. In accordance with one embodiment of the invention, a single-ended switch mode RF amplifier includes an RF input signal; an active device having a control terminal; and a non-resonant driving circuit for receiving the RF input signal and controlling a signal applied to the control terminal so as to operate the active device in switch mode.

Abstract: The present invention, generally speaking, provides a PLL that enables smooth switching of loop bandwidth without changing the loop filter. In accordance with one aspect of the invention, the loop bandwidth of a phase lock loop including an output frequency divider and a reference frequency divider is changed by changing a divisor of the output frequency divider by a factor and changing a divisor of the reference frequency divider by substantially the same factor. If the factor is greater than one, the loop bandwidth is decreased. If the factor is less than one, then the loop bandwidth is increased. In accordance with another aspect of the invention, a phase lock loop includes an oscillator having a control input, a phase comparator, a loop filter, and a feedback path including an output frequency divider. A reference frequency divider is also provided.

Abstract: The present invention, generally speaking, provides a quadrature-free RF receiver for directly receiving RF signals such as angle modulated signals. Various embodiments of the receiver use a digital phase detector together with well-known RF components: a limiter, an envelope detector, a slow Automatic Gain Control (AGC) circuit, a fast AGC circuit, etc. Demodulation may be non-coherent or coherent. The approach followed is to handle the underlying non-linearities of the demodulation process within the circuitry itself, rather than relegating the non-linearities to a separate signal processing step as in the prior art. No I and Q signals are obtained, and no coordinate conversions are performed, offering the potential for space savings, increased accuracy, and especially power savings. Depending on the nature of the modulation employed, either circuitry relating to amplitude recovery or circuitry relating to phase recovery may be dispensed with.

Abstract: The present invention, generally speaking, provides improved methods of generating clean, precisely-modulated waveforms, at least partly using digital techniques. In accordance with one aspect of the invention, a "difference engine" is provided that produces a digital signal representing the frequency error between a numeric frequency and an analog frequency. The frequency error may be digitally integrated to produce a digital signal representing the phase error. The difference engine may be incorporated into a PLL, where the analog frequency is that of an output signal of a VCO of the PLL. Direct modulation of the PLL output signal may be performed numerically. By further providing an auxiliary modulation path and performing calibration between the direct modulation path and the auxiliary modulation path, modulation characteristics may be separated from loop bandwidth constraints.