Abstract: A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circuit blocks. The method includes the steps of registering measurement terminals as cells in design rules, together with the circuit blocks wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device, and the measurement terminal is connectable to a wiring line for connecting any two of the circuit blocks, which is formed in any layer of the semiconductor device; planar-arranging the measurement terminals and the circuit blocks; and establishing connection of each wiring line, which extends from one of the circuit blocks, via one of the measurement terminals.

Abstract: The present invention provides an LSI inspection method and a defect inspection data analysis apparatus capable of shortening a time needed for a wafer test. In a first database 11 is stored inspection data obtained when each defect inspection apparatus 20 inspects a wafer for defects in the front-end process. In a second database 12 are stored non-conforming article judgment criteria for each predetermined type of defect, according to which a non-conforming chip is judged. A defective chip identifying portion 16 identifies a chip having a defect and identifies the type of defect for each defect that the identified chip has, on the basis of the inspection data. For each identified chip, a non-conforming chip judging portion 17 judges whether the chip is a non-conforming article or not according to the non-conforming article judgment criteria corresponding to the type of defect for each defect, and obtains position information within the wafer surface of a chip judged as being a non-conforming article.

Abstract: A method of making a semiconductor device by forming bumps on pads of a test piece. The method includes a fastening process of pouring a bump material including a liquid and a plurality of individual pump materials toward a target face of a mask substrate, the mask substrate having a plurality of holding holes, and making bump materials to become fastened to the holding holes; a removing process of removing the individual bump materials remaining on the target face from the target face; and a compression process of compressing the pads of the test piece from the side of the target face of the mask substrate toward the mask substrate so as to bond the individual bump materials onto the pads. By this method, micro bump materials can be accurately attached onto pads on a silicon wafer, or the like, and the size of the mask substrate can be easily increased.

Abstract: A semiconductor device capable of reducing its size and increasing the number of chips on a wafer, and a method of manufacturing the same are provided. When manufacturing a semiconductor device, an uppermost layer as a dedicated layer for pads are formed above a layer in which power supply/ground wiring lines and wiring lines for supplying associated control signals to a memory cell unit and a control circuit are formed. The uppermost layer of the semiconductor device is comprised only of a plurality of pads 11 as an electrode for providing electrical connection with an external connection line for transmitting a signal to and from the semiconductor device, a plurality of contact holes 12 for providing electrical connection with lower wiring lines formed in a lower layer below the uppermost layer, and uppermost wiring lines 13 for connecting the plurality of pads 11 to the plurality of contact holes 12 correspondingly.

Abstract: The present invention provides an LSI inspection method and a defect inspection data analysis apparatus capable of shortening a time needed for a wafer test. In a first database 11 is stored inspection data obtained when each defect inspection apparatus 20 inspects a wafer for defects in the front-end process. In a second database 12 are stored non-conforming article judgment criteria for each predetermined type of defect, according to which a non-conforming chip is judged. A defective chip identifying portion 16 identifies a chip having a defect and identifies the type of defect for each defect that the identified chip has, on the basis of the inspection data. For each identified chip, a non-conforming chip judging portion 17 judges whether the chip is a non-conforming article or not according to the non-conforming article judgment criteria corresponding to the type of defect for each defect, and obtains position information within the wafer surface of a chip judged as being a non-conforming article.

Abstract: Filters that have transmission wavelength characteristics that change in stages are provided. An object being inspected is specified based on spectrum characteristics that are created from image data of images that have passed through the filters and been picked up by a CCD camera. The image data as well as the spectrum characteristic data are recorded as a database on a hard disk. Then, a comparison is made between this database and the data of the object being inspected.

Abstract: The present invention provides an LSI inspection method and a defect inspection data analysis apparatus capable of shortening a time needed for a wafer test. In a first database 11 is stored inspection data obtained when each defect inspection apparatus 20 inspects a wafer for defects in the front-end process. In a second database 12 are stored non-conforming article judgment criteria for each predetermined type of defect, according to which a non-conforming chip is judged. A defective chip identifying portion 16 identifies a chip having a defect and identifies the type of defect for each defect that the identified chip has, on the basis of the inspection data. For each identified chip, a non-conforming chip judging portion 17 judges whether the chip is a non-conforming article or not according to the non-conforming article judgment criteria corresponding to the type of defect for each defect, and obtains position information within the wafer surface of a chip judged as being a non-conforming article.

Abstract: A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circuit blocks. The method includes the steps of registering measurement terminals as cells in design rules, together with the circuit blocks wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device, and the measurement terminal is connectable to a wiring line for connecting any two of the circuit blocks, which is formed in any layer of the semiconductor device; planar-arranging the measurement terminals and the circuit blocks; and establishing connection of each wiring line, which extends from one of the circuit blocks, via one of the measurement terminals.

Abstract: A photomask by which no electrostatic damage or damage of a mask pattern due to electrification is produced. The photomask has a substrate; mask patterns formed on the substrate, which are made of a light blocking material and are covered with a light-transmissive and electrically conductive polymer material. Even the mask patterns which are isolated from each other on the substrate are electrically conductive with each other. Typically, the mask patterns are covered with an electrically conductive film made of the light-transmissive and electrically conductive polymer material. The electrically conductive film may have a thickness by which when foreign particles land on the electrically conductive film, an optical image of the foreign particles is defocused on a sample to be exposed in the exposure process, so that shapes of the foreign particles are not transferred. In this case, a pellicle, which is conventionally provided on the substrate, is unnecessary.

Abstract: An analytical simulator and analytical simulation method and program for determining a defective portion in a device in a short time without requiring a high level of experience and skill. The simulator has a design section for designing the device based on predetermined design data including design specification data; a test result tool for receiving results of a test on the device as an object to be analyzed, where the device is designed by the design section and is produced based on the design; and an analysis section for comparing each test result with an expected output value of the object to be analyzed, where the expected output value is calculated by the design section, and for determining a range including a defective portion in the object to be analyzed, based on results of the comparison.

Abstract: The bump ball crimping apparatus of the present invention is characterized in comprising an alignment plate 31 for aligning bump balls; a crimping table 32 on which the wafer to which bump balls are to be crimped is mounted; a crimping plate 42 that crimps the bump balls onto the bonding pads of the wafer; a Y-axis moving mechanism 35 that can move the alignment plate 31 in the Y direction and can fasten it at a predetermined position; an X-axis moving mechanism that can move the alignment plate 31 in the X direction and can fasten it at a predetermined position; and a second Y-axis moving mechanism 37 that can move the crimping table 32 in the Y direction and can fasten it at a predetermined position.

Abstract: A bump forming method for forming bumps on pads of a test piece which is a semiconductor wafer or chip includes a fastening process of pouring a bump material including liquid toward a target face of a mask substrate in which a plurality of holding holes are provided, and making bump materials, included in the bump material including liquid, be fastened to the holding holes; a removing process of removing bump materials remaining on the target face of the mask substrate; and a compression process of compressing the pads of the test piece from the side of the target face of the mask substrate toward the mask substrate so as to bond the bump materials onto the pads. Micro bump materials can be accurately attached onto pads on a silicon wafer, or the like, and the size of the mask substrate can be easily increased.

Abstract: A bump forming method and apparatus by which no deformed bump having an abnormal shape is formed and no shape correcting process is necessary, the member for handling the bump materials can be easily changed, and the position of the member after the change of the member can be easily adjusted with a desired accuracy, thereby shortening the bump forming process and reducing the manufacturing cost. A positioning member is set above a heating device. Bump materials are inserted into positioning holes of the positioning member and are made to partially protrude from the holes toward a side opposite to the heating device. A semiconductor substrate is positioned onto the positioning member so that the semiconductor substrate faces the protruding side of the bump materials. The bump materials are heated and pressed from the protruding side via the semiconductor substrate so as to form bumps having a specific shape.

Abstract: In a method for manufacturing a semiconductor device according to the present invention, a back surface on a silicon wafer is ground and, after that, mirror-finished. A breakable layer on a back surface is removed. A silicon wafer is formed in the silicon wafer has a back surface in which a crystalline layer which is disposed innermore than the breakable layer is exposed. Bumps are formed on predetermined positions on a surface on the silicon wafer. By doing this, it is possible to provide a semiconductor device and a method for manufacturing therefore in which it is possible to prevent a crack from being formed on the semiconductor base board caused by a stress in a process for forming the bumps. As a result, it is possible to improve the production yield in the process for forming the bumps. Also, it is possible to realize more integration in the semiconductor device by a lower production cost.

Abstract: A production process for a semiconductor apparatus is provided in which there is no danger of particle generation, and consequently no danger of associated problems resulting from the presence of particles, such as shorting, and which as a result, is capable of producing improved product yields, good product quality stability and improved product reliability. A resist 13b is formed on those regions of a N-type silicon substrate 1 on which wiring is not to be formed, a conductive layer 15 is formed across the entire surface of the N-type silicon substrate 1 including the resist 13b, and the conductive layer 15 is then polished by mechanical polishing, as this result, the surface of the resist 13b is exposed.

Abstract: A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circuit blocks. The method includes the steps of registering measurement terminals as cells in design rules, together with the circuit blocks wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device, and the measurement terminal is connectable to a wiring line for connecting any two of the circuit blocks, which is formed in any layer of the semiconductor device; planar-arranging the measurement terminals and the circuit blocks; and establishing connection of each wiring line, which extends from one of the circuit blocks, via one of the measurement terminals.

Abstract: The present invention provides an LSI inspection method and a defect inspection data analysis apparatus capable of shortening a time needed for a wafer test. In a first database 11 is stored inspection data obtained when each defect inspection apparatus 20 inspects a wafer for defects in the front-end process. In a second database 12 are stored non-conforming article judgment criteria for each predetermined type of defect, according to which a non-conforming chip is judged. A defective chip identifying portion 16 identifies a chip having a defect and identifies the type of defect for each defect that the identified chip has, on the basis of the inspection data. For each identified chip, a non-conforming chip judging portion 17 judges whether the chip is a non-conforming article or not according to the non-conforming article judgment criteria corresponding to the type of defect for each defect, and obtains position information within the wafer surface of a chip judged as being a non-conforming article.

Abstract: A semiconductor memory apparatus that stores data by accumulating charges in its capacitor is provided for allowing itself to be operated at a low potential and at a high speed. In the semiconductor memory apparatus, before performing a precharge by a precharging circuit 10 for the next cycle of read and write, a forced step-down circuit 11 previously lowers the potential of the bit line BL charged on the high side to a level within the range of preventing data of positive charges written and stored in a memory cell MC from being disappeared.

Abstract: This invention provides a cantilever type probe card which has undergone a treatment for facilitating perception of the image of probe needles. This invention, in the probe card 1 having disposed at prescribed positions on the probe card main body 2 such probe needles 3 furnished with bent pars 6 having the leading terminals thereof directed toward an object under test, forms in a at least the parts of the probe needles 3 including the bent parts 6 such reflection lowering parts 31 adapted to repress the reflection of light.

Abstract: The present invention provides a semiconductor device production method that eliminates the risk of the occurrence of residual resist in the production process, and as a result, allows the electrical characteristics and reliability of the device to be improved. In this semiconductor device production method comprising steps of: subsequently laminating a first resist layer and a second resist layer having desired patterns on a semiconductor substrate, forming a first conductive region on the semiconductor substrate by injecting a first ion into the semiconductor substrate using the first and second resist layers as masks, removing the second resist layer, forming a second conductive region on the semiconductor substrate by injecting a second ion into the semiconductor substrate using the remaining first resist layer as a mask, and removing the first resist layer.