Abstract: The bump ball crimping apparatus of the present invention is characterized in comprising an alignment plate 31 for aligning bump balls; a crimping table 32 on which the wafer to which bump balls are to be crimped is mounted; a crimping plate 42 that crimps the bump balls onto the bonding pads of the wafer; a Y-axis moving mechanism 35 that can move the alignment plate 31 in the Y direction and can fasten it at a predetermined position; an X-axis moving mechanism that can move the alignment plate 31 in the X direction and can fasten it at a predetermined position; and a second Y-axis moving mechanism 37 that can move the crimping table 32 in the Y direction and can fasten it at a predetermined position.

Abstract: A bump forming method and apparatus by which no deformed bump having an abnormal shape is formed and no shape correcting process is necessary, the member for handling the bump materials can be easily changed, and the position of the member after the change of the member can be easily adjusted with a desired accuracy, thereby shortening the bump forming process and reducing the manufacturing cost. A positioning member is set above a heating device. Bump materials are inserted into positioning holes of the positioning member and are made to partially protrude from the holes toward a side opposite to the heating device. A semiconductor substrate is positioned onto the positioning member so that the semiconductor substrate faces the protruding side of the bump materials. The bump materials are heated and pressed from the protruding side via the semiconductor substrate so as to form bumps having a specific shape.

Abstract: An electronic CAD system for producing layout data by using data of a predetermined pattern, which employs a novel set of data attributes for reducing the amount of layout data. The system has a layout data production processing unit for producing the following data as the layout data: identification data for a polygon used for designating an area where a plurality of the predetermined patterns are arranged; a set of vertex coordinates of the polygon; identification data of the predetermined pattern; and data for defining intervals at which the predetermined patterns are arranged. Even when patterns are arranged in an undefined area having a shape which cannot be represented by a simple array of the patterns, the array representation is performed by employing the set of vertex coordinates of a polygon for designating an area where the patterns are arranged.

Abstract: A photomask by which no electrostatic damage or damage of a mask pattern due to electrification is produced. The photomask has a substrate; mask patterns formed on the substrate, which are made of a light blocking material and are covered with a light-transmissive and electrically conductive polymer material. Even the mask patterns which are isolated from each other on the substrate are electrically conductive with each other. Typically, the mask patterns are covered with an electrically conductive film made of the light-transmissive and electrically conductive polymer material. The electrically conductive film may have a thickness by which when foreign particles land on the electrically conductive film, an optical image of the foreign particles is defocused on a sample to be exposed in the exposure process, so that shapes of the foreign particles are not transferred. In this case, a pellicle, which is conventionally provided on the substrate, is unnecessary.

Abstract: A semiconductor memory apparatus that stores data by accumulating charges in its capacitor is provided for allowing itself to be operated at a low potential and at a high speed. In the semiconductor memory apparatus, before performing a precharge by a precharging circuit 10 for the next cycle of read and write, a forced step-down circuit 11 previously lowers the potential of the bit line BL charged on the high side to a level within the range of preventing data of positive charges written and stored in a memory cell MC from being disappeared.

Abstract: In a method for manufacturing a semiconductor device according to the present invention, a back surface on a silicon wafer is ground and, after that, mirror-finished. A breakable layer on a back surface is removed. A silicon wafer is formed in the silicon wafer has a back surface in which a crystalline layer which is disposed innermore than the breakable layer is exposed. Bumps are formed on predetermined positions on a surface on the silicon wafer. By doing this, it is possible to provide a semiconductor device and a method for manufacturing therefore in which it is possible to prevent a crack from being formed on the semiconductor base board caused by a stress in a process for forming the bumps. As a result, it is possible to improve the production yield in the process for forming the bumps. Also, it is possible to realize more integration in the semiconductor device by a lower production cost.

Abstract: A method for manufacturing a semiconductor device enables the formation of a well optimized for a fine MOS transistor and a well formed deep with a relatively low concentration for a high voltage MOS transistor without increasing the number of manufacturing steps. The method for manufacturing a semiconductor device includes the steps of: forming a first ion implantation expendable film and an etching mask film on a first conductive type semiconductor substrate; patterning the etching mask film into a shape of an active and field region; introducing dopant into the substrate; forming a trench groove on the substrate; forming an insulation film in the trench groove; forming a first well; flattening the insulation film; removing the etching mask film; removing the expendable film; forming a second ion implantation expendable film on the substrate; forming a mask pattern; and forming a second well by introducing dopant into the substrate.

Abstract: A test pin unit that allows a test-pin replacement at a substantially low cost. The test pin unit has a coil spring, a movable member, a retaining member, and a test pin. The movable member is capable of moving within a predetermined distance along a predetermined reference axis. The coil spring forces the movable member toward the distal end of the predetermined reference axis. The retaining member retains the test pin substantially in parallel to the reference axis in a removable manner and is integrally mounted on the movable member. In addition, the retaining member has a housing part to hold a part of the test pin and at least one screw provided on the periphery of the housing part. The test pin is fixed on the housing part by housing the part of the test pin and then securing the part of the test pin on the housing part by the screw.

Abstract: A surface of a silicon wafer having bump electrodes is divided in a matrix manner by scribe lines (2 and 3). The divided areas are silicon chips (4). A plurality of bumps 5 are formed on predetermined positions on the silicon chips (4). The bumps (5) are electrically conductive wear-resistant members so as to withstand repeated use. By doing this, it is possible to provide a semiconductor device which can realize a mounting operation for a semiconductor substrate of small size with high density at low cost and to measure electrical characteristics for semiconductor wafers and semiconductor chips efficiently in a manufacturing process or after a mounting operation.

Abstract: A semiconductor device capable of reducing its size and increasing the number of chips on a wafer, and a method of manufacturing the same are provided. When manufacturing a semiconductor device, an uppermost layer as a dedicated layer for pads are formed above a layer in which power supply/ground wiring lines and wiring lines for supplying associated control signals to a memory cell unit and a control circuit are formed. The uppermost layer of the semiconductor device is comprised only of a plurality of pads 11 as an electrode for providing electrical connection with an external connection line for transmitting a signal to and from the semiconductor device, a plurality of contact holes 12 for providing electrical connection with lower wiring lines formed in a lower layer below the uppermost layer, and uppermost wiring lines 13 for connecting the plurality of pads 11 to the plurality of contact holes 12 correspondingly.

Abstract: A semiconductor device having a silicon substrate 1 and a second electrode layer 7 directly connected with each other, and a plural number of capacitors positioning a first insulating layer 8 and a second insulating layer 6 between a first electrode layer 5 and a second electrode layer 7 and between the first electrode layer 5 and the silicon substrate 1

Abstract: A system for forming bumps on pads which are provided on a target at low cost and with high productivity. The target is a semiconductor wafer or a semiconductor chip. The system has an attracting and compressing device for attracting bump materials for bumps, and compressing and bonding the bump materials onto the pads. The attracting and compressing device may have an attracting and compressing plate in which hollow portions for attracting and holding the bump materials are formed, the hollow portions being one of holes, concave portions, and grooves. The attracting and compressing plate can collectively attract the bump materials to be compressed onto a predetermined area which corresponds to one of a wafer, a chip, and a block. The attracting and compressing device may have a finishing plate which has a flat surface for pressing and bonding the bump materials, and an ultrasonic wave generating device.

Abstract: An analytical simulator and analytical simulation method and program for determining a defective portion in a device in a short time without requiring a high level of experience and skill. The simulator has a design section for designing the device based on predetermined design data including design specification data; a test result tool for receiving results of a test on the device as an object to be analyzed, where the device is designed by the design section and is produced based on the design; and an analysis section for comparing each test result with an expected output value of the object to be analyzed, where the expected output value is calculated by the design section, and for determining a range including a defective portion in the object to be analyzed, based on results of the comparison.

Abstract: The invention provides a semiconductor memory device capable of performing a memory function test without using an expensive tester. When a test enable signal is inputted, a controller 21 makes first selectors 23a and 23b and a second selector 24 select respectively an internal row address signal, an internal column address signal and internal data obtained by utilizing a signal from a counter 22, and thereby writes internal data into each memory cell on the basis of the internal row address signal and the internal column address signal and thereafter reads data from each memory cell on the basis of the internal row address signal and the internal column address signal. A comparator 25 compares data read from each memory cell at the time of a data reading operation with expected value data obtained by utilizing a signal issued from the counter 22 at the time of the said read operation, and outputs the result of comparison.

Abstract: A method for fabricating a semiconductor device in which a wiring having a thickness with a high uniformity can be formed in the process of wiring formation using a dual damascene technology. In the method, an insulating film being patterned is formed on a semiconductor wafer, followed by forming a Cu film on both a wiring formation area which the insulating film is not formed and said insulating film. Then, the Cu film is mechanically polished until a step caused by a wiring layout is disappeared. After that, the Cu film on the insulating film is polished using chemical and mechanical polishing procedures to form a wiring made of the Cu film in the wiring formation area.

Abstract: A test pin unit that allows a test-pin replacement at a substantially low cost is provided. The test pin unit has a coil spring, a movable member, a retaining member, and a test pin. The movable member is capable of moving within a predetermined distance along a predetermined reference axis. The coil spring forces the movable member toward the distal end of the predetermined reference axis. The retaining member retains the test pin substantially in parallel to the reference axis in a removable manner and is integrally mounted on the movable member. In addition, the retaining member has a housing part for housing a part of the test pin and at least one screw provided on the periphery of the housing part. The test pin is fixed on the housing part by housing the part of the test pin and then securing the part of the test pin on the housing part by the screw.

Abstract: The present invention provides a semiconductor device production method that eliminates the risk of the occurrence of residual resist in the production process, and as a result, allows the electrical characteristics and reliability of the device to be improved. In this semiconductor device production method comprising steps of: subsequently laminating a first resist layer and a second resist layer having desired patterns on a semiconductor substrate, forming a first conductive region on the semiconductor substrate by injecting a first ion into the semiconductor substrate using the first and second resist layers as masks, removing the second resist layer, forming a second conductive region on the semiconductor substrate by injecting a second ion into the semiconductor substrate using the remaining first resist layer as a mask, and removing the first resist layer.

Abstract: A method for manufacturing a semiconductor device enables the formation of a well optimized for a fine MOS transistor and a well formed deep with a relatively low concentration for a high voltage MOS transistor without increasing the number of manufacturing steps. The method for manufacturing a semiconductor device includes the steps of: forming a first ion implantation expendable film and an etching mask film on a first conductive type semiconductor substrate; patterning the etching mask film into a shape of an active and field region; introducing dopant into the substrate; forming a trench groove on the substrate; forming an insulation film in the trench groove; forming a first well; flattening the insulation film; removing the etching mask film; removing the expendable film; forming a second ion implantation expendable film on the substrate; forming a mask pattern; and forming a second well by introducing dopant into the substrate.

Abstract: The invention provides a semiconductor memory device capable of performing a memory function test without using an expensive tester.