Patents Assigned to Unimicron Technology Corp.
  • Publication number: 20210219435
    Abstract: A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.
    Type: Application
    Filed: April 1, 2021
    Publication date: July 15, 2021
    Applicant: Unimicron Technology Corp.
    Inventors: Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
  • Patent number: 11058012
    Abstract: A circuit board structure includes a circuit layer structure, an electronic component, and a stopper. The circuit layer structure includes a plurality of dielectric layers and circuits in the dielectric layers. The electronic component is disposed in the circuit layer structure; the electronic component includes a chip and a conductive bump; the chip has a first surface and a second surface that are oppositely disposed, and the first surface of the chip contacts one of the dielectric layers; the conductive bump is on the second surface of the chip and is electrically connected to the chip. The stopper is within the circuit layer structure and abuts against the conductive bump. A method for fabricating a circuit board structure is also provided herein.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: July 6, 2021
    Assignee: Unimicron Technology Corp.
    Inventor: Chien-Chen Lin
  • Publication number: 20210202407
    Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Applicant: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Yu-Chi Shen, Tzyy-Jang Tseng, Chen-Hua Cheng, Pei-Wei Wang
  • Publication number: 20210193608
    Abstract: A manufacturing method of a circuit board element including the following steps is provided: placing a circuit substrate on a carrier, wherein the circuit substrate includes an insulating layer and a circuit layer disposed thereon, a protective layer disposed on the circuit layer and having a plurality of openings exposing thereof, and a plurality of solder balls disposed on the protective layer and embedded in the openings; forming a trench penetrating the circuit substrate to expose the carrier; forming a photoresist material layer to cover the circuit substrate and filling the spaces between each of the solder balls and the protective layer and is filling in the trench to cover the carrier; curing a portion of the photoresist material layer filled in the spaces to form a dielectric layer; removing a portion of the photoresist material layer filled in the trench to expose the carrier; and removing the carrier.
    Type: Application
    Filed: March 9, 2021
    Publication date: June 24, 2021
    Applicant: Unimicron Technology Corp.
    Inventors: Yu-Chung Hsieh, Chun-Hsien Chien, Yu-Hua Chen
  • Patent number: 11037869
    Abstract: A method of preparing a package structure is provided, which includes providing a carrier plate including a supporting layer, a first release layer, and a first metal layer; forming a first dielectric layer over the first metal layer, the first dielectric layer having a plurality of holes, each of the holes having an end portion substantially coplanar with each other at a same plane; forming a plurality of conductive protrusions filling the holes, each of the conductive protrusions having a first end and a second end opposite thereto; forming a circuit layer structure including at least one circuit layer and at least one second dielectric layer, the circuit layer being connected to the second end, the second dielectric layer being disposed over the circuit layer; removing the carrier plate; and removing a portion of the first dielectric layer to expose the conductive protrusions. A package structure is also provided.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: June 15, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Fu-Yang Chen, Chun-Hsien Chien, Cheng-Hui Wu, Wei-Ti Lin
  • Patent number: 11032917
    Abstract: A circuit carrier board includes a first substrate and a second substrate bonding to the first substrate. The first substrate includes a first circuit layer connecting to a plurality of conductive structure. The conductive structures connect to electronic elements. The second substrate contacts the first circuit layer. The second substrate includes a plurality of stacked dielectric layers, and a plurality of second circuit layers are disposed in the dielectric layers. The bottommost layer of the second circuit layers is exposed outside of the dielectric layers, and the topmost layer of the second circuit layers is electrically connected to the first circuit layer. The conductive structure includes a pad and a conductive via. The pad electrically connects to the first circuit layer. A linewidth of the first circuit layer is smaller than a linewidth of the second circuit layer. A manufacturing method of the circuit carrier board is also provided.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: June 8, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Fu-Yang Chen
  • Patent number: 11011458
    Abstract: A method of manufacturing circuit board structure includes forming a sacrificial layer having first openings on a substrate; forming a metal layer on the sacrificial layer; forming a patterned photoresist layer having second openings over the sacrificial layer, in which the second openings are connected to the first openings and expose a portion of the metal layer; forming a first circuit layer filling the second openings and the first openings; forming a first dielectric layer over the sacrificial layer and covering the metal layer, in which the first dielectric layer has third openings exposing the first circuit layer; forming a second circuit layer filling the third openings and covering a portion of the first dielectric layer; removing the substrate to expose the sacrificial layer, a portion of the metal layer and a portion of the first circuit layer; and removing the sacrificial layer and the metal layer.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: May 18, 2021
    Assignee: Unimicron Technology Corp.
    Inventor: Chien-Chen Lin
  • Patent number: 11013103
    Abstract: A method for forming a circuit board includes forming a first dielectric layer, a first circuit layer in the first dielectric layer, a second circuit layer on the first dielectric layer, and a plurality of conductive vias in the first dielectric layer and connecting the first circuit layer to the second circuit layer; forming a second dielectric layer on the first dielectric layer and the second circuit layer; forming a plurality of openings in the second dielectric layer to expose a plurality of parts of the second circuit layer; forming a seed layer on the exposed parts of the second circuit layer and sidewalls of the openings; and forming a plurality of bonding layers on the seed layer, wherein the bonding layers and the seed layer are made of copper, and the bonding layers are porous.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: May 18, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Ra-Min Tain, Kai-Ming Yang, Chien-Tsai Li
  • Publication number: 20210136931
    Abstract: A manufacturing method of a carrier structure includes: A build-up circuit layer is formed on a carrier. The build-up circuit layer includes at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on the carrier and includes at least one first pad, which is disposed relative to at least one through hole of the carrier. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive via penetrates the first dielectric layer and is electrically connected to the first circuit layer and the second circuit layer.
    Type: Application
    Filed: January 13, 2021
    Publication date: May 6, 2021
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Cheng-Ta Ko, Pu-Ju Lin, Tse-Wei Wang
  • Patent number: 10998258
    Abstract: A circuit carrier includes a substrate, a laminar circuit structure, a metal heat slug, a first fixing piece, and a second fixing piece. The laminar circuit structure is disposed over the substrate and includes a plurality of dielectric layers and circuits in the dielectric layers. The metal heat slug is disposed in the laminar circuit structure. The first fixing piece is disposed on the first side of the upper surface of the metal heat slug. The second fixing piece is disposed on the second side of the upper surface of the metal heat slug, wherein the first side is perpendicular to the second side. A method of manufacturing a circuit carrier is also provided herein.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: May 4, 2021
    Assignee: Unimicron Technology Corp.
    Inventor: Tzu-Hsuan Wang
  • Patent number: 10999935
    Abstract: A manufacturing method of a circuit board including the following steps is provided. A carrier substrate is provided. A patterned photoresist layer is formed on the carrier substrate. An adhesive layer is formed on the top surface of the patterned photoresist layer. A dielectric substrate is provided. A circuit pattern and a dielectric layer covering the circuit pattern are formed on the dielectric substrate, wherein the dielectric layer has an opening exposing a portion of the circuit pattern. The adhesive layer is adhered to the dielectric layer in a direction that the adhesive layer faces of the dielectric layer. The carrier substrate is removed. A patterned metal layer is formed on a region exposed by the patterned photoresist layer. The patterned photoresist layer is removed. The adhesive layer is removed.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: May 4, 2021
    Assignee: Unimicron Technology Corp.
    Inventor: Shih-Lian Cheng
  • Patent number: 10999939
    Abstract: A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: May 4, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
  • Patent number: 10993358
    Abstract: A device for removing a portion of cover is provided, which includes a lower platform and an upper platform oppositely disposed, a cover jig between the lower and upper platforms, a feed roller and a receiving roller oppositely disposed, and an adhesive film. The upper platform includes a plurality of protrusions, and each of the protrusions extends toward the lower platform. The cover jig includes a plurality of through holes, and each of the through holes is disposed opposite to each of the protrusions, so that each of the protrusions can be inserted through each of the through holes. One end of the adhesive film is connected to the feed roller, and the other end of the adhesive film is connected to the receiving roller, and a portion of the adhesive film between the two ends is located between the upper platform and the cover jig.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: April 27, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Chi-Shiang Chen, Bo-Han Li
  • Patent number: 10993332
    Abstract: A circuit substrate includes a substrate, a wire build-up layer structure, and an insulating layer. The substrate has a first surface and a second surface opposites to the first surface. The substrate includes a plurality of patterned pads. The patterned pads are disposed on the first surface of the substrate, and having contact openings. The wire build-up layer structure is disposed on the first surface of the substrate. The wire build-up layer structure includes an interconnect build-up layer and a plurality of conductive pillars. The conductive pillars electrically connect to the interconnect build-up layer and the patterned pads. The insulating layer is disposed between the substrate and the wire build-up layer structure.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: April 27, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Kai-Ming Yang, Chen-Hao Lin
  • Publication number: 20210118839
    Abstract: A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.
    Type: Application
    Filed: November 18, 2019
    Publication date: April 22, 2021
    Applicant: Unimicron Technology Corp.
    Inventors: Pu-Ju Lin, Cheng-Ta Ko, Ra-Min Tain, Tzyy-Jang Tseng
  • Patent number: 10978401
    Abstract: A package structure includes a first substrate, a second substrate, a plurality of dies, a plurality of first conductive elements, and a plurality of second conductive elements. The first substrate has a recessed region. The second substrate is disposed in the recessed region and protrudes from the first substrate. The dies are disposed on the first substrate and the second substrate, such that the second substrate is disposed between the first substrate and the dies. The first conductive elements are disposed between the dies and the first substrate. The dies are electrically connected with the first substrate through the first conductive elements. The second conductive elements are disposed between the dies and the second substrate. The dies are electrically connected with the second substrate through the second conductive elements.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: April 13, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Yi Lin, Chun-Ming Chiu, Hung-Chih Lee, Chang-Fu Chen
  • Patent number: 10964634
    Abstract: A circuit carrier with embedded substrate includes a circuit structure and an embedded substrate. The circuit structure includes a first dielectric layer, a first patterned circuit layer, a trench, and a plurality of first bumps. The first dielectric layer has a first surface and a second surface opposite to each other. The first patterned circuit layer is embedded in the first surface. The first bumps are disposed on the first surface and electrically connected to the first patterned circuit layer. The trench exposes a portion of the first dielectric layer. The embedded substrate is disposed in the trench and includes a plurality of second bumps. A chip package structure includes the above circuit carrier with embedded substrate.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: March 30, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Chien-Chen Lin, Tzu-Hsuan Wang, Kuan-Wen Fong
  • Patent number: 10957658
    Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: March 23, 2021
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Pu-Ju Lin, Cheng-Ta Ko, Yu-Hua Chen, Tzyy-Jang Tseng, Ra-Min Tain
  • Publication number: 20210082810
    Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 18, 2021
    Applicants: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Tao-Chih Chang, Yu-Min Lin, Sheng-Tsai Wu
  • Patent number: D919528
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: May 18, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Shih-Yao Lin, Ming-Yuan Hsu, Meng-Chia Chan, Kuo-Chuan Huang, Cheng-Jui Chang