Abstract: A package structure includes a package substrate, an application specific integrated circuit (ASIC), a plurality of optoelectronic assemblies, and a plurality of organic interposers. The ASIC is disposed on the package substrate and electrically connected to the package substrate. The optoelectronic assemblies are separately disposed on the package substrate and surround the ASIC. Each of the plurality of optoelectronic assemblies includes an electronic integrated circuit (EIC), a photonic integrated circuit (PIC), and a plurality of hybrid bonding pads. The EIC is bonded to the PIC through the plurality of hybrid bonding pads. The plurality of organic interposers are separately disposed on the package substrate and surround the ASIC. The optoelectronic assemblies are electrically connected to the package substrate through the plurality of organic interposers.

Abstract: A package structure includes a package substrate, an organic interposer and an electronic unit. The package substrate includes a plurality of first pads. The organic interposer is disposed on the package substrate and includes a plurality of second pads. The second pads are directly connected to the first pads to electrically connected the organic interposer to the package substrate. At least one of each of the first pads and each of the second pads includes a pad portion and a plurality of contact portions connecting the pad portion. A first extension direction of the pad portion is different from a second extension direction of the contact portions. The electronic unit is disposed on the organic interposer, wherein the electronic unit is electrically connected to the package substrate through the organic interposer.

Abstract: A package structure includes a package substrate, a system on a chip (SoC), at least one input/output circuit, multiple optoelectronic assemblies and an organic interposer. The SoC is disposed on the package substrate and includes a central processing unit (CPU), a graphics processing unit (GPU) and a memory. The input/output circuit is disposed on the package substrate. The optoelectronic assemblies are separately disposed on the package substrate and surround the SoC and the input/output circuit. The organic interposer is disposed on the package substrate. The SoC, the input/output circuit and the optoelectronic assemblies are electrically connected to the package substrate through the organic interposers.

Abstract: A package substrate includes a core layer, at least one functional component, at least one spacer, a filler, a first and a second build-up structures. The core layer has at least one opening and multiple conductive through vias. The functional component is disposed in the openings. The spacer is disposed on the functional component. The filler is filled in the opening, covering the functional component and spacer, and completely filling the gap between the opening, the functional component and the spacer. The first build-up structure is disposed on a first surface of the core layer and a third surface of the filler, and electrically connected to the functional component and the conductive through vias. The second build-up structure is disposed on a second surface of the core layer and a fourth surface of the filler, contacts the spacer and electrically connected to the conductive through vias.

Abstract: An inspection system and an inspection method of a bare circuit board are provided. The inspection system is used for inspecting a bare circuit board. The bare circuit board includes a chip pad and an antenna. The inspection system includes an adapter board, a test device and a measure device. The adapter board includes a chip and a contact structure. The chip is electrically connected to the contact structure. The contact structure touches the chip pad so that the chip is electrically connected to the chip pad. The test device includes a transceiver antenna. The test device and the bare circuit board separate. The measure device is electrically connected to the chip or the transceiver antenna.

Abstract: A chip package structure includes a first chip, a second chip, a plurality of first hybrid bonding pads, a first insulating layer, a first patterned conductive layer, a second patterned conductive layer, and a plurality of first conductive via structures and second conductive via The first chip is electrically connected to the second chip through a plurality of first 5 structures. through silicon vias. The first chip is bonded onto the second chip through the first hybrid bonding pads. The first insulating layer covers the first and the second chips. The first and the second patterned conductive layers are respectively disposed on a first upper surface and a first lower surface of the first insulating layer. The first conductive via structures are electrically connected to the first and the second patterned conductive layers. The second conductive via structures are electrically connected to the first chip and the first patterned conductive layer.

Abstract: An integrated circuit (IC) package structure includes a chip, a redistribution layer (RDL) structure, a molding compound structure and an electromagnetic interference (EMI) shielding structure. The RDL structure is formed on the chip and electrically connected thereto. The molding compound layer is provided on outer surfaces of the chip and the RDL structure. The EMI shielding structure is provided on outer surfaces of the molding compound structure. The molding compound structure layer provided on outer surfaces of the chip and the RDL structure provide protection and reinforcement to multiple faces of the IC package structure; and the EMI shielding structure provided on outer surfaces of the molding compound structure provides EMI protection to multiple faces of the chip and the RDL structure.

Abstract: A connector and a manufacturing method thereof. The connector includes at least one circuit substrate, at least one contact and a first elastic body. The at least one circuit substrate has a first surface. The at least one contact includes a fixed part and a first contact part that are connected to each other. The fixed part is disposed on the at least one circuit substrate. The first contact part protrudes out of the first surface and covers a part of the first surface. The first elastic body is disposed on the first surface and is electrically insulated. At least a part of the first elastic body is located between the first contact part and the first surface.

Abstract: An electronic packaging structure including a first circuit structure and a second circuit structure is provided. An electronic component is disposed between the first circuit structure and the second circuit structure. At least one of the first circuit structure and the second circuit structure (for example, the second circuit structure) has a cavity. The electronic component is embedded in the cavity, and may be encapsulated between the first circuit structure and the second circuit structure.

Abstract: A light-emitting diode package structure includes a heat dissipation substrate, a redistribution layer, and multiple light-emitting diodes. The heat dissipation substrate includes multiple copper blocks and a heat-conducting material layer. The copper blocks penetrate the heat-conducting material layer. The redistribution layer is disposed on the heat dissipation substrate and electrically connected to the copper blocks. The light-emitting diodes are disposed on the redistribution layer and are electrically connected to the redistribution layer. A side of the light-emitting diodes away from the redistribution layer is not in contact with any component.

Abstract: An electronic device including a light-emitting element, an IC chip, a substrate, an optical waveguide layer, and an optical signal outlet is provided. The IC chip is configured to control the light-emitting element to emit an optical signal. The light-emitting element is disposed on a first surface of the substrate, and the IC chip is disposed on a second surface of the substrate. The optical waveguide layer is disposed on the first surface of the substrate, and the optical waveguide layer includes a core layer, a cladding layer, and a metal layer. The metal layer is disposed on at least a portion of an interface between the core layer and the cladding layer. The optical signal outlet corresponds to the light-emitting element, and the optical signal reaches the optical signal outlet after being transmitted in the core layer.

Abstract: Provided is a circuit board structure including a substrate, a loop-wrapping ground layer, an insulating structure, a first build-up layer, a top wiring layer, a bottom wiring layer, a first conductive via, and a plurality of second conductive vias. The aforementioned structure defines a signal transmitting structure. An equivalent circuit of the signal transmitting structure at least includes a first equivalent circuit, a second equivalent circuit, a third equivalent circuit and a fourth equivalent circuit, which correspond to different uniform transmitting sections respectively. The first equivalent circuit, the second equivalent circuit, the third equivalent circuit and the fourth equivalent circuit are connected in series with each other according to an ABCD transmission matrix series connection principle.

Abstract: A circuit board structure includes a core, a wiring layer and a buried passive component. The wiring layer and the buried passive component are disposed on the core, and the buried passive component is electrically connected to the wiring layer. The buried passive component includes a first spiral metal layer, a second spiral metal layer and a dielectric interlayer. The first spiral metal layer is intertwined with the second spiral metal layer. The dielectric interlayer is disposed between the first spiral metal layer and the second spiral metal layer. The first spiral metal layer and the second spiral metal layer are spaced apart by the dielectric interlayer at least in the core.

Abstract: A substrate structure and a cutting method thereof are provided. The cutting method includes the following steps. A first substrate structure is provided, wherein the first substrate structure includes a glass substrate and a redistribution layer disposed on the glass substrate. A laser process is performed on the glass substrate to form a modified region on the glass substrate. A wet etching process is performed on the modified region of the glass substrate to remove the modified region and form a plurality of second substrate structures.

Abstract: A circuit substrate structure includes a circuit substrate, at least two chips, and a bridge element. The circuit substrate has a first surface and a second surface opposite to each other. The chips are arranged in parallel on the first surface of the circuit substrate and electrically connected to the circuit substrate. The chips have active surfaces, back surfaces opposite to the active surfaces, and side surfaces connecting the active surfaces and the back surfaces. The chips include side circuits. The side circuits are arranged on the side surfaces and have first ends and second ends, the first ends extend to the active surfaces along the side surfaces, and the second ends extend to the back surfaces along the side surfaces. The bridge element is arranged on the back surfaces of the chips and electrically connected to the active surfaces of the chips through the side circuits.

Abstract: A manufacturing method of the circuit board includes the following. The third substrate has an opening and includes a first, a second and a third dielectric layers. The opening penetrates the first and the second dielectric layers, and the opening is fully filled with the third dielectric layer. The first, the second and the third substrates are press-fitted so that the second substrate is located between the first and the third substrates. Multiple conductive structures are formed so that the first, the second and the third substrates are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, and the third dielectric layer of the third substrate. The conductive via structure is electrically connected to the first and the third substrates to define a signal path. The ground path surrounds the signal path.

Abstract: The invention discloses a glass carrier having a protection structure, comprising a glass body and a protection layer. The glass body has a top surface, a bottom surface, and a lateral surface. The protection layer covers the lateral surface of the glass body. The protection layer is a hard material with a stiffness coefficient higher than a stiffness coefficient of the glass body. The invention further discloses a manufacturing method of a glass carrier having a protection structure, comprising the following steps: covering the protection layer around the lateral surface of the glass body, wherein the protection layer is the hard material with the stiffness coefficient higher than the stiffness coefficient of the glass body.

Abstract: A bare circuit board is provided, in which the bare circuit board includes a substrate, an antenna, a chip pad, a ground pattern and a trace. The substrate includes a surface. The antenna and the chip pad are formed on the substrate. The ground pattern is formed on the surface. The trace is formed on the surface and isn't connected to the ground pattern. A measuring gap is formed between the trace and an edge of the ground pattern, and the trace includes a first end and a second end. The first end is electrically connected to the chip pad, whereas the second end is electrically connected to the antenna. The bare circuit board is adapted to transmit a signal. The width of the measuring gap is smaller than a quarter of an equivalent wavelength of the signal.

Abstract: A circuit carrier includes at least one wiring layer and a capacitive element. The capacitive element is disposed in at least one dielectric layer of the wiring layer. The capacitive element includes a lower electrode, an inter-electrode and an upper electrode. The inter-electrode is located between the lower electrode and the upper electrode. The inter-electrode includes a plate, at least one first finger and at least one second finger. The first finger and the second finger extend from opposite sides of the plate, respectively.

Abstract: A manufacturing method of the package carrier includes the following steps. A circuit substrate having a through via is provided. A heat-conducting material layer coving the inner wall of the through via is electroplated on the circuit substrate. A first build-up structure and a second build-up structure are respectively formed on two opposite sides of the circuit substrate. Parts of the first build-up structure, the circuit substrate, the heat-conducting material layer and the second build-up structure are removed to expose the remaining heat-conducting material layer, so as to define a heat-conducting element and form a circuit structure layer including a notch portion. The heat-conducting element includes a first heat-conducting portion and a second heat-conducting portion vertically connected to the first heat-conducting portion.