Patents Assigned to Unimicron Technology Corp.
  • Publication number: 20200266181
    Abstract: A manufacturing method of the light-emitting diode package structure is provided. A carrier is formed. The carrier comprises a first build-up circuit. At least one self-assembled material layer is formed on the first build-up circuit. A first solder mask layer is formed on the first build-up circuit. The first solder mask layer has at least one opening to expose a portion of the at least one self-assembled material layer. At least one light-emitting diode is disposed on the first build-up circuit. The at least one light-emitting diode has a self-assembled pattern, and the at least one light-emitting diode is self-assembled into the at least one opening of the first solder mask layer through a force between the self-assembled pattern and the at least one self-assembled material layer.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 20, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Fu-Yang Chen
  • Patent number: 10736215
    Abstract: A multilayer circuit board structure includes a first multilayer circuit board and a second multilayer circuit board. The first multilayer circuit board includes a first patterned circuit layer and a first dummy circuit layer. The first dummy circuit layer surrounds the first patterned circuit layer. The second multilayer circuit board is disposed on the first multilayer circuit board, and includes a second patterned circuit layer and a second dummy circuit layer surrounding the second patterned circuit layer. The first patterned circuit layer is bonded to the second patterned circuit layer and the first dummy circuit layer is bonded to the second dummy circuit layer. A hollow space is defined between the first multilayer circuit board and the second multilayer circuit board.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: August 4, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Shao-Chien Lee, Ming-Hao Wu, Zong-Hua Li
  • Patent number: 10729014
    Abstract: A method for manufacturing a circuit board includes forming a patterned first dielectric layer on a substrate; forming a first adhesive layer on the patterned first dielectric layer; forming a second dielectric layer on the first adhesive layer; patterning the second dielectric layer to expose a portion of a top surface of the first adhesive layer opposite to the substrate; and filling at least the patterned second dielectric layer with a conductive material, such that the conductive material is in contact with the top surface of the first adhesive layer.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: July 28, 2020
    Assignee: Unimicron Technology Corp.
    Inventor: Po-Hsuan Liao
  • Patent number: 10714448
    Abstract: A chip module includes a body, a bump, and a first bonding layer. The bump is disposed on the body. The first bonding layer is disposed on the bump. The first bonding layers and the bump are made of the same conductive material and the first bonding layer is porous.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 14, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Chin-Sheng Wang, Ra-Min Tain
  • Patent number: 10700049
    Abstract: A light-emitting diode package structure includes a carrier, at least one self-assembled material layer, a first solder mask layer, and at least one light-emitting diode. The carrier includes a first build-up circuit. The self-assembled material layer is disposed on the first build-up circuit. The first solder mask layer is disposed on the first build-up circuit. The first solder mask layer has at least one opening to expose a portion of the self-assembled material layer. The light-emitting diode is disposed on the first build-up circuit. The light-emitting diode has a self-assembled pattern. The light-emitting diode is self-assembled into the opening of the first solder mask layer through a force between the self-assembled pattern and the self-assembled material layer. A manufacturing method of the light-emitting diode package structure is also provided.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: June 30, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Fu-Yang Chen
  • Patent number: 10700161
    Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. A substrate structure obtained by the manufacturing method of the substrate structure is provided.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 30, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Fu-Yang Chen, Chun-Hsien Chien, Chien-Chou Chen, Wei-Ti Lin
  • Publication number: 20200194384
    Abstract: A substrate structure includes a glass substrate, a first circuit layer, a second circuit layer, and at least one conductive region. The glass substrate has a first surface and a second surface opposing the first surface. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The conductive region includes a plurality of conductive micro vias. The conductive micro vias penetrate through the glass substrate. The conductive micro vias are electrically connected to the first circuit layer and the second circuit layer, and the conductive micro vias have a via size of 2 ?m to 10 ?m.
    Type: Application
    Filed: November 5, 2019
    Publication date: June 18, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Chun-Hsien Chien, Po-Chen Lin, Wen-Liang Yeh, Chien-Chou Chen
  • Publication number: 20200196440
    Abstract: A composite substrate structure includes a circuit substrate, a first anisotropic conductive film, a first glass substrate, a dielectric layer, a patterned circuit layer and a conductive via. The first anisotropic conductive film is disposed on the circuit substrate. The first glass substrate is disposed on the first anisotropic conductive film and has a first surface and a second surface opposite to the first surface. The first glass substrate includes a first circuit layer, a second circuit layer and at least one first conductive via. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The first conductive via penetrates the first glass substrate and is electrically connected to the first circuit layer and the second circuit layer. The first glass substrate and the circuit substrate are respectively located on two opposite sides of the first anisotropic conductive film.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 18, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Pei-Wei Wang, Bo-Cheng Lin, Chun-Hsien Chien, Chien-Chou Chen
  • Patent number: 10685922
    Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: June 16, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Pu-Ju Lin, Cheng-Ta Ko, Yu-Hua Chen, Tzyy-Jang Tseng, Ra-Min Tain
  • Patent number: 10673194
    Abstract: A manufacturing method of connector structure including the following steps is provided. First, providing a dielectric layer having. Then, forming a first adhesive layer and a second adhesive layer on two opposite sides of the dielectric layer respectively. Then, providing at least one first conductive elastic cantilever and at least one second conductive elastic cantilever, wherein the first conductive elastic cantilever comprises a first fixing end portion and a first free end portion, and the second conductive elastic cantilever comprises a second fixing end portion and a second free end portion. Then, fixing the first fixing end portion and the second fixing end portion to the first adhesive layer and the second adhesive layer respectively, wherein the first fixing end portion is aligned with the second fixing end portion. Afterward, forming at least one conductive via for electrically connecting the first conductive elastic cantilever with the second conductive elastic cantilever.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 2, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Hsiang Chuang, Guodong Li, He Lei, Jianyu Zhang
  • Patent number: 10667406
    Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.
    Type: Grant
    Filed: September 16, 2018
    Date of Patent: May 26, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Cheng-Chieh Chiu, Chia-Chan Chang, Chun-Yi Kuo, Yu-Cheng Lin
  • Publication number: 20200161518
    Abstract: A light-emitting diode package including a carrier structure, a patterned conductive layer, at least one chip, a dielectric layer, at least one first conductive via, a build-up circuit structure, and at least one light-emitting diode is provided. The patterned conductive layer is disposed on the carrier structure. The chip is disposed on the carrier structure. The dielectric layer is disposed on the carrier structure and encapsulates the chip and the patterned conductive layer. The first conductive via penetrates the dielectric layer and is electrically connected to the patterned conductive layer. The build-up circuit structure is disposed on the dielectric layer and electrically connected to the first conductive via. The light-emitting diode is disposed on the build-up circuit structure.
    Type: Application
    Filed: February 21, 2019
    Publication date: May 21, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Yi-Cheng Lin, Yu-Hua Chen, Chun-Hsien Chien, Chien-Chou Chen, Cheng-Hui Wu
  • Publication number: 20200163215
    Abstract: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 21, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Wen-Liang Yeh, Chun-Hsien Chien, Chien-Chou Chen, Cheng-Hui Wu
  • Patent number: 10658282
    Abstract: A package substrate structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The vias and the pads are disposed on the first substrate, and fills the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar is disposed between the first substrate and the second substrate, where each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills the gaps between the conductive pillars. A bonding method of the package substrate structure is also provided.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: May 19, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Cheng-Ta Ko, Kai-Ming Yang, Yu-Hua Chen, Tzyy-Jang Tseng
  • Patent number: 10660202
    Abstract: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 19, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Wen-Liang Yeh, Chun-Hsien Chien, Chien-Chou Chen, Cheng-Hui Wu
  • Publication number: 20200154578
    Abstract: A circuit substrate includes a substrate, a wire build-up layer structure, and an insulating layer. The substrate has a first surface and a second surface opposites to the first surface. The substrate includes a plurality of patterned pads. The patterned pads are disposed on the first surface of the substrate, and having contact openings. The wire build-up layer structure is disposed on the first surface of the substrate. The wire build-up layer structure includes an interconnect build-up layer and a plurality of conductive pillars. The conductive pillars electrically connect to the interconnect build-up layer and the patterned pads. The insulating layer is disposed between the substrate and the wire build-up layer structure.
    Type: Application
    Filed: January 20, 2020
    Publication date: May 14, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Kai-Ming Yang, Chen-Hao Lin
  • Patent number: 10651358
    Abstract: A light emitting device package structure includes a substrate, a circuit layer structure, a light emitting device, a first redistribution layer, a conductive connector, a second redistribution layer, and a chip. The circuit layer structure is disposed over the substrate, and the circuit layer structure includes a first circuit layer. The light emitting device is disposed over the circuit layer structure and is electrically connected with the first circuit layer. The first redistribution layer is disposed over the light emitting device and includes a second circuit layer and a conductive contact contacting the second circuit layer. The conductive connector connects the first circuit layer and the second circuit layer. The second redistribution layer is disposed over the first redistribution layer and includes a third circuit layer contacting the conductive contact. The chip is disposed over the second redistribution layer and is electrically connected with the third circuit layer.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 12, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Pei-Wei Wang, Cheng-Ta Ko, Yu-Hua Chen, De-Shiang Liu, Tzyy-Jang Tseng
  • Patent number: 10629511
    Abstract: A heat dissipation substrate includes an inner circuit structure, a first build-up circuit structure and a heat dissipation channel. The first build-up circuit structure is disposed on the inner circuit structure, and includes an interlayer dielectric layer, a first dielectric layer, a first patterned conductive layer and a plurality of first conductive vias. The first patterned conductive layer and the first dielectric layer are sequentially stacked on the interlayer dielectric layer. The heat dissipation channel is disposed around the chip disposing area on the first build-up circuit structure and has a first opening and a second opening. The first opening penetrates through the first dielectric layer and exposes a portion of the interlayer dielectric layer. The second opening is disposed on a side surface of the first build-up circuit structure. The first opening is in communication with the second opening.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: April 21, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Chien-Chen Lin, Tzu-Hsuan Wang
  • Patent number: 10615054
    Abstract: A method for manufacturing conductive lines is provided. A first metal layer is formed over a carrier substrate. A second metal layer is formed over the first metal layer. A plurality of first conductive lines is formed on the second metal layer. A protective layer is formed on opposite sidewalls of the first conductive lines. An exposed portion of the second metal layer is removed to expose a portion of the first metal layer. The exposed portion of the first metal layer is removed, and the protective layer is removed.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: April 7, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventor: Shih-Liang Cheng
  • Patent number: 10616992
    Abstract: A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: April 7, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Yin-Ju Chen, Ming-Hao Wu, Cheng-Po Yu