Patents Assigned to Unimicron Technology Corporation
  • Patent number: 10820411
    Abstract: A manufacturing method for a circuit board and a circuit board are provided. The method includes steps: providing a substrate having a first metal layer; forming a patterned first opening on the first metal layer to expose the substrate; forming a patterned first dielectric layer on the substrate, the first dielectric layer is made of a photosensitive dielectric material and covers the first opening; photosensitizing the first dielectric layer to cure the first dielectric layer; forming a patterned second metal layer on the first metal layer; forming a patterned third metal layer on the second metal layer, and the third metal layer being adjacent to the first dielectric layer; removing a portion of the first metal layer not covered by the second metal layer; and forming a second dielectric layer on the substrate. A thickness of the third metal layer is greater than a thickness of the second metal layer.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: October 27, 2020
    Assignee: Unimicron Technology Corporation
    Inventors: Shih-Lian Cheng, Zhe-Yong Lin, Li-Jie Liu, Ching Sheng Chen
  • Patent number: 9433108
    Abstract: A method for fabricating a circuit board structure having at least an embedded electronic element is disclosed, which includes the steps of: providing a substrate and embedding at least an electronic element in the substrate with an active surface and a plurality of electrode pads of the electronic element exposed from a surface of the substrate; forming a plurality of conductive bumps on the electrode pads of the electronic element; and covering the surface of the substrate and the active surface of the electronic element with a dielectric layer and a metal layer stacked on the dielectric layer, wherein the conductive bumps penetrate the dielectric layer so as to be in contact with the metal layer, thereby simplifying the fabrication process, reducing the fabrication cost and saving the fabrication time.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: August 30, 2016
    Assignee: Unimicron Technology Corporation
    Inventors: Yung-Ching Lin, Chih-Kuie Yang, Ta-Han Lin
  • Patent number: 9385056
    Abstract: A packaging substrate includes a carrier and an interposer. The carrier has opposite top and bottom surfaces. A recess is formed on the top surface and a plurality of first conductive terminals are formed on the recess. Further, a plurality of second conductive terminals are formed on the bottom surface of the carrier. The interposer is disposed in the recess and has opposite first and second surfaces and a plurality of conductive through vias penetrating the first and second surfaces. A first conductive pad is formed on an end of each of the conductive through vias exposed from the first surface, and a second conductive pad is formed on the other end of each of the conductive through vias exposed from the second surface and electrically connected to a corresponding one of the first conductive terminals. Compared with the prior art, the invention improves the product reliability.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: July 5, 2016
    Assignees: Unimicron Technology Corporation, Industrial Technology Research Institute
    Inventors: Dyi-Chung Hu, John Hon-Shing Lau
  • Patent number: 9362140
    Abstract: A package stack device includes a first package structure having a plurality of first metal posts and a first electronic element, a second package structure having a plurality of second metal posts and a second electronic element, and an encapsulant formed between the first and second package structures to encapsulate the first electronic element. By connecting the second metal posts to the first metal posts, respectively, the second package structure is stacked on the first package structure with the support of the metal posts. Further, the gap between the two package structures is filled with the encapsulant to avoid warpage of the substrates.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: June 7, 2016
    Assignee: Unimicron Technology Corporation
    Inventor: Dyi-Chung Hu
  • Patent number: 9357659
    Abstract: A packaging substrate having an embedded through-via interposer is provided, including an encapsulant layer, a through-via interposer embedded in the encapsulant layer and having a plurality of conductive through-vias therein, a redistribution layer embedded in the encapsulant layer and formed on the through-via interposer so as to electrically connect with first end surfaces of the conductive through-vias, and a built-up structure formed on the encapsulant layer and the through-via interposer for electrically connecting second end surfaces of the conductive through-vias.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: May 31, 2016
    Assignee: Unimicron Technology Corporation
    Inventors: Dyi-Chung Hu, Tzyy-Jang Tseng
  • Patent number: 9337136
    Abstract: A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: May 10, 2016
    Assignee: Unimicron Technology Corporation
    Inventors: Tzyy-Jang Tseng, Dyi-Chung Hu, Ying-Chih Chan
  • Patent number: 9295159
    Abstract: A packaging substrate with an embedded semiconductor component and a method of fabricating the same are provided, including: fixing a semiconductor chip with electrode pads to an assisting layer with apertures through an adhesive member, wherein each of the electrode pads has a bump formed thereon, each of the apertures is filled with a filling material, and the bumps correspond to the apertures, respectively; forming a first dielectric layer on the assisting layer to encapsulate the semiconductor chip; removing the bumps and the filling material to form vias; and forming a first wiring layer on the first dielectric layer and forming first conductive vias in the vias to provide electrical connections between the electrode pads and the first wiring layer, wherein the first wiring layer comprises a plurality of conductive lands formed right on the first conductive vias, respectively.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: March 22, 2016
    Assignee: Unimicron Technology Corporation
    Inventor: Zhao Chong Zeng
  • Patent number: 9257379
    Abstract: A coreless packaging substrate is provided which includes: a circuit buildup structure having at least a dielectric layer, at least a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the lowermost one of the at least a dielectric layer, a plurality of metal bumps formed on the uppermost one of the at least a wiring layer, and a dielectric passivation layer formed on the surface of the uppermost one of the circuit buildup structure and the metal bumps, with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip is enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: February 9, 2016
    Assignee: Unimicron Technology Corporation
    Inventors: Tzyy-Jang Tseng, Chung-W. Ho
  • Patent number: 9230895
    Abstract: A package substrate includes: a dielectric layer having two opposite surfaces; a wiring layer embedded in the dielectric layer and exposed from the two opposite surfaces of the dielectric layer, wherein the wiring layer has solder pads, conductive pads and circuit wires electrically connecting the solder pads and the conductive pads; and a first insulating protection layer disposed on one of the two opposite surfaces of the dielectric layer to cover the dielectric layer and the wiring layer and having a plurality of openings for exposing the conductive pads, respectively. The package substrate, by directly using the dielectric layer as a base, provides a package substrate having reduced thickness and lower fabrication costs compared to the prior art.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: January 5, 2016
    Assignee: Unimicron Technology Corporation
    Inventors: Pao-Hung Chou, Hsien-Min Chang
  • Patent number: 9232665
    Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: January 5, 2016
    Assignee: Unimicron Technology Corporation
    Inventors: Shih-Ping Hsu, Zhao-Chong Zeng
  • Patent number: 9230899
    Abstract: A packaging substrate includes a holder, a first conductive pad disposed on the holder, a core layer disposed on the holder, a circuit layer disposed on the core layer, a plurality of conductive vias disposed in the core layer, and an insulating protection layer disposed on the core layer, wherein the first electrical pad is embedded in the core layer. By combining the holder on one side of the packaging substrate, cracks due to over-thinness can be prevented during transferring or packaging. A method of fabricating the packaging substrate, a package structure having a holder, a method of fabricating the package structure are also provided.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: January 5, 2016
    Assignee: Unimicron Technology Corporation
    Inventors: Wen-Lung Lai, Yuan-Liang Lo
  • Patent number: 9224683
    Abstract: A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: December 29, 2015
    Assignee: Unimicron Technology Corporation
    Inventors: Tzyy-Jang Tseng, Dyi-Chung Hu, Ying-Chih Chan
  • Patent number: 9179549
    Abstract: A packaging substrate includes: a core board with at least a cavity; a dielectric layer unit having upper and lower surfaces and encapsulating the core board and filling the cavity; a plurality of positioning pads embedded in the lower surface of the dielectric layer unit; at least a passive component having upper and lower surfaces with electrode pads disposed thereon and embedded in the dielectric layer unit so as to be received in the cavity of the core board at a position corresponding to the positioning pads; first and second wiring layers disposed on the upper and lower surfaces of the dielectric layer unit and electrically connected to the electrode pads of the upper and lower surfaces of the passive component through conductive vias, respectively. By embedding the passive component in the core board and the dielectric layer unit, the invention effectively reduces the height of the overall structure.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: November 3, 2015
    Assignee: Unimicron Technology Corporation
    Inventors: Shih-Ping Hsu, Zhao-Chong Zeng
  • Patent number: 9129870
    Abstract: A package structure having an embedded electronic component includes: a carrier having a cavity penetrating therethrough; a semiconductor chip received in the cavity and having solder bumps disposed thereon; a dielectric layer formed on the carrier and the semiconductor chip so as to encapsulate the solder bumps; a wiring layer formed on the dielectric layer; an insulating protection layer formed on the dielectric layer and the wiring layer; and a solder material formed in the dielectric layer and the insulating protection layer for electrically connecting the wiring layer and the solder bumps, thereby shortening the signal transmission path between the semiconductor chip and the carrier to avoid signal losses.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: September 8, 2015
    Assignee: Unimicron Technology Corporation
    Inventor: Zhao-Chong Zeng
  • Patent number: 9111948
    Abstract: A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: August 18, 2015
    Assignee: Unimicron Technology Corporation
    Inventors: Tzyy-Jang Tseng, Dyi-Chung Hu, Yu-Shan Hu
  • Patent number: 9111818
    Abstract: A packaging substrate is provided, including a substrate body having a plurality of conductive pads, an insulating protective layer formed on the substrate body for the conductive pads to be exposed therefrom, and a plurality of conductive pillars disposed on the conductive pads. Each of the conductive pillars has a bottom end and a top end narrower than the bottom end, thereby forming a cone-shaped structure that does not have a wing structure. Therefore, the distance between contact points is reduced and the demands for fine-pitch and multi-joints are satisfied.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: August 18, 2015
    Assignee: Unimicron Technology Corporation
    Inventors: Chun-Ting Lin, Yu-Chung Hsieh, Ying-Tung Wang, Ying-Chih Chan
  • Patent number: 9093459
    Abstract: A package structure includes: a first dielectric layer having a first surface and a second surface opposing the first surface; a semiconductor chip embedded in the first dielectric layer in a manner that the semiconductor chip protrudes from the second surface, and having an active surface and an inactive surface opposing the active surface, electrode pads being disposed on the active surface and in the first dielectric layer, the inactive surface and a part of a side surface adjacent the inactive surface protruding from the second surface; a first circuit layer disposed on the first surface; a built-up structure disposed on the first surface and the first circuit layer; and an insulating protective layer disposed on the built-up structure, a plurality of cavities being formed in the insulating protective layer for exposing a part of a surface of the built-up structure. The package structure includes only one built-up structure.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 28, 2015
    Assignee: Unimicron Technology Corporation
    Inventors: Pao-Hung Chou, Chih-Hao Hsu
  • Patent number: 9070616
    Abstract: A packaging substrate includes a first dielectric layer; a plurality of first conductive pads embedded in and exposed from a first surface of the first dielectric layer; a first circuit layer embedded in and exposed from a second surface of the first dielectric layer; a plurality of first metal bumps disposed in the first dielectric layer, each of the first metal bumps having a first end embedded in the first circuit layer and a second end opposing the first end and disposed on one of the first conductive pads, a conductive seedlayer being disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump; a built-up structure disposed on the first circuit layer and the first dielectric layer; and a plurality of second conductive pads disposed on the built-up structure. The packaging substrate has an over-warpage problem improved.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: June 30, 2015
    Assignee: Unimicron Technology Corporation
    Inventors: Tzyy-Jang Tseng, Chung-W. Ho
  • Patent number: 9024422
    Abstract: A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: May 5, 2015
    Assignee: Unimicron Technology Corporation
    Inventors: Shih-Ping Hsu, I-Ta Tsai
  • Patent number: 8999759
    Abstract: A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; forming a first metallic frame around the periphery of the opening on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: April 7, 2015
    Assignee: Unimicron Technology Corporation
    Inventor: Kan-Jung Chia