Abstract: A coreless packaging substrate is provided which includes: a circuit buildup structure having at least a dielectric layer, at least a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the lowermost one of the at least a dielectric layer, a plurality of metal bumps formed on the uppermost one of the at least a wiring layer, and a dielectric passivation layer formed on the surface of the uppermost one of the circuit buildup structure and the metal bumps, with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip is enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.

Abstract: A coreless package substrate is provided, including: a circuit buildup structure including at least a dielectric layer, at least a circuit layer and conductive elements; first electrical contact pads embedded in the lowermost dielectric layer of the circuit buildup structure; a plurality of metal bumps formed on the uppermost circuit layer of the circuit buildup structure; a dielectric passivation layer disposed on a top surface of the circuit buildup structure and the metal bumps; and second electrical contact pads embedded in the dielectric passivation layer and electrically connected to the metal bumps. With the second electrical contact pads being engaged with the metal bumps and having top surfaces thereof completely exposed, the bonding strength between the second electrical contact pads and a chip to be mounted thereon and between the second electrical contact pads and the metal bumps can be enhanced.

Abstract: A packaging substrate includes a first dielectric layer, a first circuit layer, a first metal bump, and a built-up structure. The first metal bump and the first circuit layer are embedded in and exposed from two surfaces of the first dielectric layer. The end of the first metal bump is embedded in the first circuit layer and between the first circuit layer and the first dielectric layer. In addition, a conductive seedlayer is disposed between the first circuit layer and the first metal bump. The built-up structure is disposed on the first circuit layer and the first dielectric layer. The outmost layer of the built-up structure has a plurality of conductive pads. Compared to the prior art, the present invention can effectively improve the warpage problem of the conventional packaging substrate.

Abstract: A packaging structure is provided which includes: a substrate, at least an electronic module, and an adhesive material. The substrate has two opposing surfaces, at least an opening penetrating the two surfaces, and two metallic frames formed on two opening ends of the at least an opening. The electronic module is disposed in the opening and has electronic elements and an encapsulant encapsulating the electronic elements. Each of the electronic elements has two opposing active surfaces exposed from the encapsulant and electrode pads formed on the two opposing active surfaces. The electrode pads are exposed from the opening. The adhesive material is filled into the opening and a gap between the electronic module and the opening, so as to secure in position the electronic modules in the opening. Compared with the prior art, the embedded electronic elements of the packaging structure according to the present invention is prevented from short circuit, and thus has increased yield rate.

Abstract: A packaging substrate with an embedded semiconductor component and a method of fabricating the same are provided, including: fixing a semiconductor chip with electrode pads to an assisting layer with apertures through an adhesive member, wherein each of the electrode pads has a bump formed thereon, each of the apertures is filled with a filling material, and the bumps correspond to the apertures, respectively; forming a first dielectric layer on the assisting layer to encapsulate the semiconductor chip; removing the bumps and the filling material to form vias; and forming a first wiring layer on the first dielectric layer and forming first conductive vias in the vias to provide electrical connections between the electrode pads and the first wiring layer, wherein the first wiring layer comprises a plurality of conductive lands formed right on the first conductive vias, respectively.

Abstract: Provided are a circuit board structure and a fabrication method thereof, including the steps of: forming a first circuit layer in a first dielectric layer and exposing the first circuit layer therefrom; forming a second dielectric layer on the first dielectric layer and the first circuit layer, and forming a second circuit layer on the second dielectric layer; forming a plurality of first conductive vias in the second dielectric layer for electrically connecting to the first circuit layer to thereby dispense with a core board and electroplated holes and thus facilitate miniaturization. Further, the first dielectric layer is liquid before being hardened and is formed on the first dielectric layer that enhances the bonding between layers of the circuit board and the structure.

Abstract: A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect.

Abstract: A package structure having an embedded electronic component includes: a carrier having a cavity penetrating therethrough; a semiconductor chip received in the cavity and having solder bumps disposed thereon; a dielectric layer formed on the carrier and the semiconductor chip so as to encapsulate the solder bumps; a wiring layer formed on the dielectric layer; an insulating protection layer formed on the dielectric layer and the wiring layer; and a solder material formed in the dielectric layer and the insulating protection layer for electrically connecting the wiring layer and the solder bumps, thereby shortening the signal transmission path between the semiconductor chip and the carrier to avoid signal losses.

Abstract: A packaging substrate includes a core board having a first surface and an opposite second surface; at least a conic through hole formed in the core board and penetrating the first and second surfaces; a plurality of conductive paths formed on a wall of the conic through hole, free from being electrically connected to one another in the conic through hole; and a plurality of first circuits and second circuits disposed on the first and second surfaces of the core board, respectively, and being in contact with peripheries of two ends of the conic through hole, wherein each of the first circuits is electrically connected through each of the conductive paths to each of the second circuits. Compared to the prior art, the packaging substrate has a reduced number of through holes or vias and an increased overall layout density.

Abstract: A packaging substrate having a through-holed interposer embedded therein is provided, which includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer. By embedding the through-holed interposer in the molding layer and forming the built-up structure on the second surface of the molding layer, the present invention eliminates the need of a core board and reduces the thickness of the overall structure. Further, since the through-holed interposer has a CIE close to or the same as that of a silicon wafer, the structural reliability during thermal cycle testing is improved.

Abstract: A package structure, a method of fabricating the package structure, and a package-on-package device are provided, where the package structure includes a metal sheet having perforations and a semiconductor chip including an active surface having electrode pads thereon, where the semiconductor chip is combined with the metal sheet via an inactive surface thereof. Also, a protective buffer layer is formed on the active surface to cover the conductive bumps, and the perforations are arranged around a periphery of the inactive surface of the semiconductor chip. Further, an encapsulant is formed on the metal sheet and in the perforations, for encapsulating the semiconductor chip and exposing the protective buffer layer; and a circuit fan-out layer is formed on the encapsulant and the protective buffer layer and having conductive vias penetrating the protective buffer layer and electrically connecting to the conductive bumps.

Abstract: A package structure is provided that includes a metal plate; a semiconductor chip having an active surface, electrode pads disposed on the active surface, conductive bumps disposed on the electrode pads, and an inactive surface opposing the active surface and attached with the metal plate by a thermal conductive adhesive; an encapsulant formed on the metal plate for encapsulating a perimeter of the semiconductor chip, with the active surface of the semiconductor chip being exposed thereon; a first dielectric layer formed on the encapsulant and the active surface of the semiconductor chip, and having wiring trenches for exposing the conductive bumps; and a first wiring layer formed in the wiring trenches of the first dielectric layer and electrically connected to the conductive bumps. The wiring layer, through the electrical connection of the conductive bumps with the semiconductor chip prevents the use of bonding wires as a conductive pathway.

Abstract: A packaging substrate with an embedded semiconductor component and a method of fabricating the same are provided, including: fixing a semiconductor chip with electrode pads to an assisting layer with apertures through an adhesive member, wherein each of the electrode pads has a bump formed thereon, each of the apertures is filled with a filling material, and the bumps correspond to the apertures, respectively; forming a first dielectric layer on the assisting layer to encapsulate the semiconductor chip; removing the bumps and the filling material to form vias; and forming a first wiring layer on the first dielectric layer and forming first conductive vias in the vias to provide electrical connections between the electrode pads and the first wiring layer, wherein the first wiring layer comprises a plurality of conductive lands formed right on the first conductive vias, respectively.

Abstract: A package stack device includes a first package structure having a plurality of first metal posts and a first electronic element disposed on a surface thereof, a second package structure having a plurality of second metal posts and a second electronic element disposed on opposite surfaces thereof, and an encapsulant formed between the first and second package structures for encapsulating the first electronic element. By connecting the first and second metal posts, the second package structure is stacked on the first package structure with the support of the metal posts and the encapsulant filling the gap therebetween so as to prevent warpage of the substrate.

Abstract: A coreless packaging substrate includes: a substrate body including an auxiliary dielectric layer having opposing first and second surfaces, an inner wiring formed on the second surface, and a built-up structure formed on both the second surface of the auxiliary dielectric layer and the inner wiring; and a plurality of conductive bumps including metal pillars having opposing first and second ends and a solder layer formed on the first end, wherein the second ends of the metal pillars are disposed in the auxiliary dielectric layer and electrically connecting with the inner wiring, and the first ends of the metal pillars with the solder layer protrude from the first surface of the auxiliary dielectric layer, thereby achieving ultra-fine pitch and even-height conductive bumps. A method for fabricating the coreless packaging substrate as described above is further provided.

Abstract: Provided is a fabrication method of a package structure, including cutting a full-panel packaging substrate into a plurality of packaging substrate blocks, each of which has a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate units and securing and protecting the semiconductor chips with an encapsulating material, thereby forming a plurality of packaging substrate blocks with packaging substrate units; and cutting the packaging substrate blocks to separate the packaging substrate units from each other.

Abstract: A package substrate includes a core board having a through hole; a circuit layer formed on the core board; a metallic ring disposed on the core board surrounding a contour of the through hole, the metallic ring having opening portions positioned opposite to each other, making the metallic ring having a disconnected manner; and an embedded component installed in the through hole. When the embedded component is deviated in the through hole to allow the electrodes to be in contact with the metallic ring, the electrodes are prevented from coming into contact with the same section of the metallic ring to thereby avoid short circuit.

Abstract: A packaging substrate is proposed, which includes: a circuit layer formed on a substrate and having conductive pads, an insulating protective layer formed on the substrate for covering the circuit layer and having openings for correspondingly exposing the conductive pads; copper bumps each having a connection portion formed in a corresponding one of the openings and electrically connected to a corresponding one of the conductive pads, and a protruding portion integrally connected to the connection portion and extending to a portion of the insulating protective layer surrounding the corresponding one of the openings, allowing the protruding portion to be greater in diameter than the connection portion, and a surface treatment layer having an electroplated nickel material formed on top surfaces of the protruding portions of the copper bumps, and an electroplated gold material formed on the electroplated nickel material.

Abstract: A packaging substrate having a through-holed interposer embedded therein is provided, which includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer. By embedding the through-holed interposer in the molding layer and forming the built-up structure on the second surface of the molding layer, the present invention eliminates the need of a core board and reduces the thickness of the overall structure. Further, since the through-holed interposer has a CIE close to or the same as that of a silicon wafer, the structural reliability during thermal cycle testing is improved.

Abstract: A package structure includes: a first dielectric layer having a first surface and a second surface opposing the first surface; a semiconductor chip embedded in the first dielectric layer in a manner that the semiconductor chip protrudes from the second surface, and having an active surface and an inactive surface opposing the active surface, electrode pads being disposed on the active surface and in the first dielectric layer, the inactive surface and a part of a side surface adjacent the inactive surface protruding from the second surface; a first circuit layer disposed on the first surface; a built-up structure disposed on the first surface and the first circuit layer; and an insulating protective layer disposed on the built-up structure, a plurality of cavities being formed in the insulating protective layer for exposing a part of a surface of the built-up structure. The package structure includes only one built-up structure.