Patents Assigned to Unisantis Electronics
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Patent number: 11309426Abstract: An SGT circuit includes a first conductor layer which contains a semiconductor atom, which is in contact with an N+ region and a P+ region of a Si pillar, or a TiN layer, and whose outer circumference is located outside an outer circumference of a SiO2 layer in plan view, and a second conductor layer which contains a metal atom, which is connected to an outer periphery of the first conductor layer, and which extends in a horizontal direction.Type: GrantFiled: September 24, 2019Date of Patent: April 19, 2022Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada
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Patent number: 11282958Abstract: An SGT is formed that includes Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.Type: GrantFiled: March 27, 2020Date of Patent: March 22, 2022Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada
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Patent number: 11211488Abstract: An SGT is formed that includes Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.Type: GrantFiled: December 16, 2019Date of Patent: December 28, 2021Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada
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Patent number: 11183582Abstract: The method for producing a pillar-shaped semiconductor device includes a step of providing a structure that includes, on an i layer substrate, a Si pillar and an impurity region located in a lower portion of the Si pillar and serving as a source or a drain, a step of forming a SiO2 layer that extends in a horizontal direction and is connected to an entire periphery of the impurity region in plan view, a step of forming a SiO2 layer on the SiO2 layer such that the SiO2 layer surrounds the Si pillar in plan view, a step of forming a resist layer that is partly connected to the SiO2 layer in plan view, and a step of forming a SiO2 layer by etching the SiO2 layer below the SiO2 layer and the resist layer using the SiO2 layer and the resist layer as masks.Type: GrantFiled: December 6, 2019Date of Patent: November 23, 2021Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada
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Patent number: 10937902Abstract: A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer, and a second step of, after the first step, forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to achieve planarization, forming, in a direction perpendicular to a direction of the fin-shaped semiconductor layer, a second resist for forming a first gate line and a first pillar-shaped semiconductor layer and a third resist for forming a first contact line and a second pillar-shaped semiconductor layer, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form the first pillar-shaped semiconductor layer, a first dummy gate formed from the first polysilicon, the second pillar-shaped semiconductor layer, and a second dummy gate formed from the first polysilicon.Type: GrantFiled: May 2, 2018Date of Patent: March 2, 2021Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 10734391Abstract: A first contact hole is formed so as to extend to a NiSi layer as a lower wiring conductor layer connecting to an N+ layer of an SGT formed within a Si pillar, and so as to extend through a NiSi layer as an upper wiring conductor layer connecting to a gate TiN layer, and a NiSi layer as an intermediate wiring conductor layer connecting to an N+ layer. A second contact hole is formed so as to extend to the NiSi layer, and surround, in plan view, the first contact hole. An insulating SiO2 layer is formed on a side surface of the NiSi layer. A wiring metal layer in the contact holes connects the NiSi layer and the NiSi layer to each other.Type: GrantFiled: January 3, 2019Date of Patent: August 4, 2020Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada
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Patent number: 10644151Abstract: A surround gate MOS transistor (SGT) includes a silicon pillar and tungsten silicide or cobalt silicide wiring alloy layers constituted by first alloy regions connected to the entire peripheries of impurity regions serving as sources or drains in lower portions of the silicon pillar. The first alloy regions are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atoms as the impurity regions. A second alloy region is partly connected to the peripheries of the first alloy regions and contains the same impurity atoms as the impurity regions.Type: GrantFiled: April 30, 2019Date of Patent: May 5, 2020Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada
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Patent number: 10312110Abstract: A method for manufacturing a semiconductor device includes forming an SGT in a semiconductor pillar on a semiconductor substrate and forming a wiring semiconductor layer so as to contact a side surface of an impurity region present in a center portion of the semiconductor pillar or a side surface of a gate conductor layer. A first alloy layer formed in a side surface of the wiring semiconductor layer is directly connected to the impurity region and the gate conductor layer and is connected to an output wiring metal layer through a contact hole formed on an upper surface of a second alloy layer formed in an upper surface and the side surface of the wiring semiconductor layer.Type: GrantFiled: November 23, 2016Date of Patent: June 4, 2019Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada
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Patent number: 10311945Abstract: A semiconductor device constituting a decoder circuit for memory selection and having a smaller area is provided by using surrounding gate transistors (SGTs), which are vertical transistors. In a decoder circuit formed by a plurality of MOS transistors arranged in m rows and n columns, the MOS transistors that constitute the decoder circuit are arranged on a planar silicon layer formed on a substrate. Each has a structure including a drain, a gate, and a source arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer is formed by a first active region of a first conductivity type and a second active region of a second conductivity type, and the regions are connected to each other via a silicide layer formed on the surface of the planar silicon layer. Consequently, a semiconductor device that constitutes a decoder circuit having a smaller area is provided.Type: GrantFiled: October 19, 2015Date of Patent: June 4, 2019Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Masamichi Asano
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Patent number: 10103154Abstract: A method for producing an SGT-including semiconductor device includes forming a gate insulating layer on an outer periphery of a Si pillar, forming a gate conductor layer on the gate insulating layer, and forming an oxide layer on the gate conductor layer. Then a hydrogen fluoride ion diffusion layer containing hydrogen fluoride ions is formed so as to make contact with the oxide layer and lie at an intermediate position of the Si pillar. A part of the oxide film in contact with the hydrogen fluoride ion diffusion layer is etched and an opening is thereby formed on the outer periphery of the Si pillar.Type: GrantFiled: July 3, 2017Date of Patent: October 16, 2018Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada
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Patent number: 10002934Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.Type: GrantFiled: January 22, 2015Date of Patent: June 19, 2018Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura
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Patent number: 9929341Abstract: A semiconductor device includes first pillar-shaped semiconductor layers, a first gate insulating film formed around the first pillar-shaped semiconductor layers, gate electrodes formed around the first gate insulating film, gate lines connected to the gate electrodes, a second gate insulating film formed around upper portions of the first pillar-shaped semiconductor layers, first contacts formed of a first metal material and formed around the second gate insulating film, second contacts formed of a second metal material and connecting upper portions of the first contacts and upper portions of the first pillar-shaped semiconductor layers, diffusion layers formed in lower portions of the first pillar-shaped semiconductor layers, pillar-shaped insulator layers formed on the second contacts, variable-resistance films formed around upper portions of the pillar-shaped insulator layers, and lower electrodes formed around lower portions of the pillar-shaped insulator layers and connected to the variable-resistance fType: GrantFiled: April 17, 2017Date of Patent: March 27, 2018Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 9905755Abstract: A semiconductor device includes first pillar-shaped silicon layers, a first gate insulating film formed around the first pillar-shaped silicon layers, gate electrodes formed of metal and formed around the first gate insulating film, gate lines formed of metal and connected to the gate electrodes, a second gate insulating film formed around upper portions of the first pillar-shaped silicon layers, first contacts formed of a first metal material and formed around the second gate insulating film, second contacts formed of a second metal material and connecting upper portions of the first contacts and upper portions of the first pillar-shaped silicon layers, diffusion layers formed in lower portions of the first pillar-shaped silicon layers, and variable-resistance memory elements formed on the second contacts.Type: GrantFiled: April 17, 2017Date of Patent: February 27, 2018Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 9716092Abstract: A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NAND circuit. The NAND circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NAND circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NAND circuit.Type: GrantFiled: October 27, 2016Date of Patent: July 25, 2017Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Masamichi Asano
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Patent number: 9660051Abstract: A method for producing a semiconductor device includes forming a first insulating film around a fin-shaped semiconductor layer and forming a pillar-shaped semiconductor layer and forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer. A metal-semiconductor compound is formed on the second diffusion layer. A first metal is deposited to form a gate electrode and a gate line. Second and third metal films are deposited to form a first contact in which the second metal film surrounds a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second contact connects an upper portion of the first contact and an upper portion of the pillar-shaped semiconductor layer. A third contact is formed on the gate line.Type: GrantFiled: January 10, 2017Date of Patent: May 23, 2017Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 9646991Abstract: A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NOR circuit. The NOR circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NOR circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NOR circuit.Type: GrantFiled: November 4, 2015Date of Patent: May 9, 2017Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Masamichi Asano
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Patent number: 9640585Abstract: A semiconductor device includes four or more first memory cells arranged on a row, the first memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film formed around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film, and a first magnetic tunnel junction storage element formed on the first pillar-shaped semiconductor layer. The semiconductor device further includes a first source line that connects lower portions of the first pillar-shaped semiconductor layers to each other, a first bit line that extends in a direction perpendicular to a direction in which the first gate line extends and that is connected to an upper portion of the first magnetic tunnel junction storage element, and a second source line that extends in a direction perpendicular to a direction in which the first source line extends.Type: GrantFiled: December 28, 2016Date of Patent: May 2, 2017Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 9620564Abstract: A semiconductor device includes four or more first memory cells arranged on a row, the first memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film formed around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film, and a first magnetic tunnel junction storage element formed on the first pillar-shaped semiconductor layer. The semiconductor device further includes a first source line that connects lower portions of the first pillar-shaped semiconductor layers to each other, a first bit line that extends in a direction perpendicular to a direction in which the first gate line extends and that is connected to an upper portion of the first magnetic tunnel junction storage element, and a second source line that extends in a direction perpendicular to a direction in which the first source line extends.Type: GrantFiled: April 8, 2016Date of Patent: April 11, 2017Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 9613827Abstract: A method for manufacturing a semiconductor device includes forming an SGT in a semiconductor pillar on a semiconductor substrate and forming a wiring semiconductor layer so as to contact a side surface of an impurity region present in a center portion of the semiconductor pillar or a side surface of a gate conductor layer. A first alloy layer formed in a side surface of the wiring semiconductor layer is directly connected to the impurity region and the gate conductor layer and is connected to an output wiring metal layer through a contact hole formed on an upper surface of a second alloy layer formed in an upper surface and the side surface of the wiring semiconductor layer.Type: GrantFiled: October 10, 2014Date of Patent: April 4, 2017Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada
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Patent number: 9601505Abstract: A semiconductor device includes a first selection gate insulating film surrounding a first pillar-shaped semiconductor layer, a first selection gate surrounding the first selection gate insulating film, a first bit line connected to the first pillar-shaped semiconductor layer, a layer including a first charge storage layer which surrounds a second pillar-shaped semiconductor layer, a first control gate surrounding the layer, a layer including a second charge storage layer which surrounds the second pillar-shaped semiconductor layer, a second control gate surrounding the layer, a first lower-portion internal line connecting the first and second pillar-shaped semiconductor layers, a layer including a third charge storage layer, a third control gate, a layer including a fourth charge storage layer, a fourth control gate, a second selection gate insulating film, a second selection gate, a first source line, and a second lower-portion internal line.Type: GrantFiled: January 14, 2015Date of Patent: March 21, 2017Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura