Abstract: A semiconductor device has a small area and constitutes a CMOS 3-input NAND circuit by using surrounding gate transistors (SGTs) that are vertical transistors. In a 3-input NAND circuit including six MOS transistors arranged in a line, the MOS transistors constituting the NAND circuit have the following configuration. Planar silicon layers are disposed on a substrate. The drain, gate, and source of the MOS transistors are arranged in a vertical direction, and the gate surrounds a silicon pillar. The planer silicon layers include a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicide layer disposed on surfaces of the planar silicon layers. In this way, a semiconductor device constituting a NAND circuit with a small area is provided.

Abstract: A semiconductor device includes four or more memory cells arranged on a row, the memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film around the semiconductor layer, a first gate line around the first gate insulating film, a third gate insulating film around an upper portion of the semiconductor layer, a first contact electrode around the third gate insulating film, a second contact electrode connecting upper portions of the semiconductor layer and the first contact electrode, and a magnetic tunnel junction storage element on the second contact electrode, a first source line connecting lower portions of the semiconductor layers to each other, a first bit line extending in a direction perpendicular to a direction of the first gate line and connected to an upper portion of the storage element, and a second source line extending in a direction perpendicular to the first source line.

Abstract: A method for producing an SGT-including semiconductor device includes forming a gate insulating layer on an outer periphery of a Si pillar, forming a gate conductor layer on the gate insulating layer, and forming an oxide layer on the gate conductor layer. Then a hydrogen fluoride ion diffusion layer containing moisture is formed so as to make contact with the oxide layer and lie at an intermediate position of the Si pillar. A part of the oxide film in contact with the hydrogen fluoride ion diffusion layer is etched with hydrogen fluoride ions generated from hydrogen fluoride gas supplied to the hydrogen fluoride ion diffusion layer and an opening is thereby formed on the outer periphery of the Si pillar.

Abstract: A semiconductor device includes a two-input NAND circuit including four MOS transistors arranged in a line. Each of the MOS transistors is disposed on a planar silicon layer disposed on a substrate. The drain, gate, and source of the MOS transistor are arranged in the vertical direction. The gate surrounds a silicon pillar. The planar silicon layer is constituted by a first activation region of a first conductivity type and a second activation region of a second conductivity type. The first and second activation regions are connected to each other via a silicon layer disposed on a surface of the planar silicon layer, so as to form a NAND circuit having a small area.

Abstract: A semiconductor device includes a P+ region and an N+ region functioning as sources of SGTs and disposed in top portions of Si pillars formed on an i-layer substrate. Connections between a power supply wiring metal layer and the P+ region and between a ground wiring metal layer and the N+ region are established on the entire surfaces of low-resistance Ni silicide layers that are respectively in contact with the P+ region and the N+ region and formed on outer peripheries of the Si pillars. Lower ends of the power supply wiring metal layer and the ground wiring metal layer are located at a height of surfaces of HfO layers near the boundaries between the P+ region and a channel and between the N+ region and a channel, respectively.

Abstract: A semiconductor device has a small area and constitutes a CMOS 3-input NOR circuit by using surrounding gate transistors (SGTs) which are vertical transistors. In the 3-input NOR circuit including six MOS transistors arranged in a line, the MOS transistors constituting the NOR circuit have the following configuration: Planar silicon layers are disposed on a substrate. The drain, the gate, and the source of the MOS transistors are arranged in a vertical direction, and the gate surrounds a silicon pillar. The planar silicon layers include a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicide layer disposed on surfaces of the planar silicon layers. In this way, a semiconductor device constituting a NOR circuit with a small area is provided.

Abstract: A semiconductor device includes a pillar-shaped silicon layer including a first diffusion layer, a channel region, and a second diffusion layer formed in that order from the silicon substrate side, floating gates respectively disposed in two symmetrical directions so as to sandwich the pillar-shaped silicon layer, and a control gate line disposed in two symmetrical directions other than the two directions so as to sandwich the pillar-shaped silicon layer. A tunnel insulating film is formed between the pillar-shaped silicon layer and each of the floating gates. The control gate line is disposed so as to surround the floating gates and the pillar-shaped silicon layer with an inter-polysilicon insulating film interposed therebetween.

Abstract: A semiconductor device includes a P+ region and an N+ region functioning as sources of SGTs and disposed in top portions of Si pillars formed on an i-layer substrate. Connections between a power supply wiring metal layer and the P+ region and between a ground wiring metal layer and the N+ region are established on the entire surfaces of low-resistance Ni silicide layers that are respectively in contact with the P+ region and the N+ region and formed on outer peripheries of the Si pillars. Lower ends of the power supply wiring metal layer and the ground wiring metal layer are located at a height of surfaces of HfO layers near the boundaries between the P+ region and a channel and between the N+ region and a channel, respectively.

Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped silicon layer on a silicon substrate using a first resist and forming a first insulating film therearound; and a second step of forming a second insulating film around the fin-shaped silicon layer and etching the second insulating film so as to be left on a side wall of the fin-shaped silicon layer, depositing a third insulating film on the first and second insulating films and the fin-shaped silicon layer, depositing a polysilicon thereon, planarizing a surface thereof, and etching back the polysilicon to expose the third insulating film, forming a second resist, etching the second and third insulating films and then etching the fin-shaped silicon layer and the polysilicon, and removing the second insulating film to form a pillar-shaped silicon layer and a dummy gate formed of the polysilicon.

Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped silicon layer on a silicon substrate using a first resist and forming a first insulating film therearound; and a second step of forming a second insulating film around the fin-shaped silicon layer and etching the second insulating film so as to be left on a side wall of the fin-shaped silicon layer, depositing a third insulating film on the first and second insulating films and the fin-shaped silicon layer, depositing a polysilicon thereon, planarizing a surface thereof, and etching back the polysilicon to expose the third insulating film, forming a second resist, etching the second and third insulating films and then etching the fin-shaped silicon layer and the polysilicon, and removing the second insulating film to form a pillar-shaped silicon layer and a dummy gate formed of the polysilicon.

Abstract: A semiconductor device includes a pillar-shaped silicon layer including a first diffusion layer, a channel region, and a second diffusion layer formed in that order from the silicon substrate side, floating gates respectively disposed in two symmetrical directions so as to sandwich the pillar-shaped silicon layer, and a control gate line disposed in two symmetrical directions other than the two directions so as to sandwich the pillar-shaped silicon layer. A tunnel insulating film is formed between the pillar-shaped silicon layer and each of the floating gates. The control gate line is disposed so as to surround the floating gates and the pillar-shaped silicon layer with an inter-polysilicon insulating film interposed therebetween.

Abstract: An N+ region 2a and a P+ region 3a are formed in a Si pillar 6. HfO2 layers 9a and 9c, TiN layers 10b and 10d, and SiO2 layers 11b and 11d are formed to surround the Si pillar 6. Then contact portions 21a and 21b are respectively formed in side surfaces of the N+ region 2a and the P+ region 3a and a side surface of the TiN layer 10d. Then Si and Ni atoms are injected in a direction perpendicular to an upper surface of an i-layer substrate 1 from above the Si pillar 6 to form a Si layer and a Ni layer. Subsequently, a heat treatment is performed to expand NiSi layers 18a and 22 in a horizontal direction by Ni-silicidation. As a result, the NiSi layers 18a and 22 connect to the N+ region 2a and the P+ region 3a or the TiN layer 10d.

Abstract: A semiconductor device has a smaller area. That is, in a row selection decoder including MOS transistors, which selectively connect a plurality of selection signal lines to row selection lines of NAND flash memories having an SGT structure, the MOS transistors are formed on a planar silicon layer that is formed on a substrate, and each have a structure such that a drain, a gate, and a source are disposed in the vertical direction and the gate surrounds a silicon pillar. The planar silicon layer is formed of a first activation region of a first conductivity type and a second activation region of a second conductivity type, and the first and second activation regions are connected with each other via a silicide layer formed on the surface of the planar silicon layer.

Abstract: A semiconductor device includes a first fin-shaped semiconductor layer on a semiconductor substrate, a first insulating film around the first fin-shaped semiconductor layer, a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer, a first gate insulating film around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film and extending in a direction perpendicular to the first fin-shaped semiconductor layer, a second diffusion layer disposed in a lower portion of the first pillar-shaped semiconductor layer, a third gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer, a first contact electrode surrounding the third gate insulating film, a second contact electrode that connects an upper portion of the first contact electrode to an upper portion of the first pillar-shaped semiconductor layer, and a first magnetic tunnel junction memory element on the second contact electrode.

Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.

Abstract: In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line.

Abstract: A semiconductor device includes a pillar-shaped silicon layer including a first diffusion layer, a channel region, and a second diffusion layer formed in that order from the silicon substrate side, floating gates respectively disposed in two symmetrical directions so as to sandwich the pillar-shaped silicon layer, and a control gate line disposed in two symmetrical directions other than the two directions so as to sandwich the pillar-shaped silicon layer. A tunnel insulating film is formed between the pillar-shaped silicon layer and each of the floating gates. The control gate line is disposed so as to surround the floating gates and the pillar-shaped silicon layer with an inter-polysilicon insulating film interposed therebetween.

Abstract: A method of manufacturing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer, a first insulating film around the fin-shaped semiconductor layer, and a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A second step forms a gate insulating film around the pillar-shaped semiconductor layer, a gate electrode around the gate insulating film, and a gate line. A third step forms a first first-conductivity-type diffusion layer in an upper portion of the pillar-shaped semiconductor layer and a second first-conductivity-type diffusion layer in a lower portion of the pillar-shaped semiconductor layer and an upper portion of the fin-shaped semiconductor layer.

Abstract: A semiconductor device includes a fin-shaped silicon layer and a pillar-shaped silicon layer on the fin-shaped silicon layer, where a width of the pillar-shaped silicon layer is equal to a width of the fin-shaped silicon layer. Diffusion layers reside in upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and in a lower portion of the pillar-shaped silicon layer to form. A gate insulating film and a metal gate electrode are around the pillar-shaped silicon layer and a metal gate line extends in a direction perpendicular to the fin-shaped silicon layer and is connected to the metal gate electrode. A contact resides on the metal gate line and a nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except for the bottom of the contact.

Abstract: A semiconductor device includes a pillar-shaped semiconductor having an impurity concentration of 1017 cm?3 or less, a first insulator that surrounds the pillar-shaped semiconductor, a first metal that surrounds a portion of the first insulator at a first end of the pillar-shaped semiconductor, a second metal that surrounds a portion of the first insulator at the second end of the pillar-shaped semiconductor, a third metal that surrounds a portion of the first insulator in a region sandwiched between the first metal and the second metal, a second insulator formed between the first and third metals, a third insulator formed between the second and third metals, a fourth metal that connects the first metal and the one end, and a fifth metal that connects the second metal and the other end. The third metal has a work function of about 4.2 eV to about 5.0 eV.