Abstract: A method for fabricating in a non-volatile memory is provided. The method includes providing a substrate having a memory region. A stacked gate structure is formed on the substrate at the memory region. A source region is formed abutting the stacked gate structure, and an isolation structure is formed to isolate the source region, in which a drain region is also formed abutting the stacked gate structure on the opposite side but not actually related to the invention. A first spacer is formed on each sidewall of the stacked gate structure. A conductive layer is form over the substrate and is patterned to remove a portion of a conductive layer. A remaining portion of the conductive layer covers the isolation structure and the source region so as to form a source line, which has an electrical coupling to each source region belong to a same word line. The stacked gate structure is therefore exposed.

Abstract: An integrated circuit (IC) fabrication method is provided for fabricating a conductive plug, such as a contact plug or a via plug, with a low junction resistance in an integrated circuit. This method is characterized by the inclusion of a preliminary doping process to form a doped region in the exposed area through the contact opening or via opening. By conventional method, the exposed area would be formed with an undesired oxide layer or laid with undesired reactant remnants after the etching process for forming the contact opening or via opening. When being subjected to a high temperature during the subsequent deposition process, the dopant atoms in the doped region diffuse into these undesired insulative matters, thereby reducing the junction resistance of the resulting contact or via plug.

Abstract: A method of fabricating a coronary-type capacitor in integrated circuit is provided, which method helps increase the capacitance of the capacitor by forming the electrode of the capacitor with a coronary-like shape that is relatively large in surface area. In this method, a stacked structure of doped polysilicon layers and HSG polysilcon layers are formed in an alternating manner, which is then selectively removed to form a void portion. A heat-treatment process is then performed on the wafer at a temperature of about 600-700° C. to cause the impurity ions in the doped polysilicon layers to be activated and evenly diffused over the inside of the doped polysilicon layers. Finally, a selective etching process is performed with an etchant that can react with polysilicon at a faster etching rate than with HSG polysilcon so as to cause the sidewalls of the doped polysilicon layers to be more recessed than the sidewalls of the HSG polysilcon layers.

Abstract: A wafer alignment system aligns a wafer by checking the alignment marks formed on the back surface of the wafer. A number of guiding rays are used to determine the corresponding alignment mark on the back of the wafer to ensure that the wafer is properly aligned. The alignment system of the invention also includes a wafer stage and a fixed base, wherein the wafer stage and the fixed base contains a number of apertures that allow the guiding rays to pass through and strike on the alignment marks on the wafer.

Abstract: A mask includes a piece of reticle glass, a chromium thin film, a pre-alignment mark, a first alignment mark, a second alignment mark, a first identification barcode, and a second identification barcode. There is also a pellicle flame formed on the chromium thin film to prevent the patterning defects caused by particles.

Abstract: An input/output (I/O) circuit with a high I/O voltage tolerance is provided for use in conjunction with an IC device that operates with two system voltages, such as 3.3 V and 5 V. The particular circuit configuration of this I/O circuit allows it to be fabricated using the Single Gate-Oxide technology instead of the Double Gate-Oxide technology, so that the manufacturing cost can be reduced as compared to the prior art. Moreover, this I/O circuit allows an output impedance lower than that of the prior art, allowing the signal transmission speed via this I/O circuit to be increased by about 30% as compared to the prior art. It can also help eliminate the problems of poor gate oxide reliability, PN junction inversion, and PMOS leakage that otherwise occur in the prior art. Furthermore, this I/O circuit can help eliminate the DC leakage current in the input-stage circuit, so that the power consumption can be reduced compared to the prior art.

Abstract: A DRAM capacitor. A first dielectric layer is formed over a substrate having a gate and source/drain regions, and a plug penetrating through the first dielectric layer to couple with the source/drain regions. A bottom electrode comprising a vertical pole, a metal plate, a first spacer and a second spacer is formed and contacts with the plug. A second dielectric layer is formed on the bottom electrode, and then a conductive layer is formed on the second dielectric layer.

Abstract: A dual damascene process of manufacturing dual damascene structure comprising the steps of first providing a semiconductor substrate that already has an insulating layer formed thereon. Next, a trench and a via opening are formed within the insulating layer. In the subsequent step, a first glue layer, preferably a titanium layer, is formed over the trench and the via opening. Thereafter, photolithographic and etching operations are again used to remove a portion of the first glue layer in a region surrounding the trench. Consequently, a portion of the insulating layer is exposed while the trench and the via opening are still covered by the first glue layer. After that, a second glue layer, preferably a titanium nitride layer, is formed over the first glue layer and the insulating layer. Then, a metallic layer is formed over the second glue layer. The metallic layer completely fills the trench and the via opening. The second glue layer and the metallic layer have a polishing selectivity ratio of about 1:1.

Abstract: A method is provided to increase the contact area of a contact window. In this method, the contact area is mainly increased by a concavity which is formed by first forming a thin oxide layer in the contact region using local oxidation, then further by removing the thin oxide layer. Additionally, in order to reduce the contact resistance, a metal oxide layer can be selectively formed at the contact interface.

Abstract: A method for removing photoresist in a metallization process according to the invention is able to completely remove a photoresist residue remaining on the surface of a metal layer and avoids corrosion of the metal layer. In the method, a heat treatment is performed after patterning the metal layer and before removing the photoresist layer, thereby removing materials which corrode the metal layer. Therefore, corrosion to the metal layer is prevented. Next, the photoresist layer is removed by a wet strip process instead of an oxygen plasma process. As a result, the photoresist residue remaining on the surface of the metal layer cannot be oxidized into an insoluble oxide and can be completely removed.

Abstract: A slurry providing system, located between a main slurry providing system and a CMP machine, includes a providing barrel, which can either be used as a buffer tank to provide slurry to the CMP machine with interruption, or as an independent backup tank for store slurry. The providing barrel also includes an impeller to stir slurry to prevent slurry deposition, and a liquid level sensor to monitor slurry level. The slurry providing system further includes a pump to continuously provide slurry from the providing barrel when the main slurry providing system is down. There is a pressure-regulating valve between the slurry providing system and the CMP machine.

Abstract: A developer cup. The developer cup includes a bed. A central spindle is vertically and rotatably coupled to a center of the bed through an end of the central spindle. A chuck is vertically coupled to an end of the central spindle opposite to the bed end. An upper coupling is coupled to the central spindle between the chuck and the bed, wherein the chuck. A lower coupling is moveably coupled to the central spindle between the upper coupling and the bed. The annular cup has an upper wheel and a lower wheel, wherein the upper wheel is aligned with the lower wheel, the upper wheel is coupled to the lower wheel through a plurality of the brackets, and the lower wheel is smaller than the upper wheel.

Abstract: A voltage boosting circuit having an asymmetric MOS in DRAM. A gate of a first NMOS connects to a voltage source, and a source region of the first NMOS connects to a row decoder. A gate of the asymmetric NMOS connects to a drain region of the first NMOS. A drain region of the asymmetric NMOS connects to a column decoder, and a source region of the first asymmetric NMOS connects to a word line. A gate of a second NMOS connects to the column decoder, a source region of the second NMOS connects to a ground terminal and a drain region of the second NMOS connects to a source region of the first asymmetric NMOS.

Abstract: A method of fabricating a capacitor is described. A dielectric layer is formed on a substrate. A node contact opening is formed in the dielectric layer to expose a portion of the substrate. A conductive layer is formed on the dielectric layer to cover the node contact opening. A ring trench is formed in the conductive layer above the node contact opening. An oxide layer is formed to fill the ring trench. An etching stop layer is formed to cover the oxide layer, the conductive layer encircled by the oxide layer, and a portion of the oxide layer beside the oxide layer. The etching stop layer defines a capacitor area. The conductive layer exposed by the etching stop layer is removed until the dielectric layer is exposed. The oxide layer and the etching stop layer are removed to expose the remaining conductive layer. A capacitor dielectric layer and a top electrode are formed in sequence to cover the remaining conductive layer.

Abstract: A method for fabricating gate oxide includes a dilute wet oxidation process with additional nitrogen and moisture and an annealing process with a nitrogen base gas, wherein the volume of additional nitrogen is about 6-12 times of the volume of the additional moisture. The method according to the invention improves the electrical quality of the gate oxide by raising the Q.sub.bd and by reducing the leakage current of the gate oxide.

Abstract: The method of the invention starts with forming a mask on a blank wafer, wherein the mask contains a number of openings that expose a portion of the wafer. By performing a wet oxidation process, field oxide is formed on the exposed surface of the wafer. The wafer surface is then become ragged after the mask and the field oxide are removed. In order to further increase the surface area of a dummy wafer, an etching process is performed on the ragged surface after a hemispherical grained layer is formed on the ragged surface.

Abstract: A method of improving junction leakage problem as STI and Salicide processes are performed is provided. The invention is to form a protective insulating layer over STI structure and the periphery of STI structure to prevent penetration of metal ions to eliminate junction leakage problem. First a silicon substrate is provided. A source/drain region and a STI structure are formed in the substrate. A sidewall recess is formed on the upper surface of the STI trench sidewall to expose the substrate. An insulating layer is formed on STI structure, the sidewall recess and the source/drain region. The insulating layer is patterned to cover STI structure and the periphery of STI structure by photolithography and etching processes. The preferred thickness of the insulating layer is thick enough to prevent penetration of metal ions formed during the Salicide process. A Salicide process is performed on the insulating layer and the conductive region.

Abstract: A method for forming a bottom electrode of a capacitor is provided. A substrate having a conductive region is provided. A first insulation layer, a stop layer and a second insulation layer are formed on the substrate in order. The first insulation layer, the stop layer and the second insulation layer are patterned to form an opening. The opening exposes the conductive region in the substrate. A first conductive layer is formed on the second insulation layer and fills the opening, and then the first conductive layer is defined to form a plug and a metal plate. The plug can be electrically connected with the conductive region. The metal plate is used as a mask, and the second insulation layer is removed by anisotropic etching to form a third insulation layer having a first distance from the third insulation layer surface to the stop layer surface.

Abstract: A sense amplifier can be used with a high-speed IC memory device, which sense amplifier can help reduce the sensing latency during read operations to the memory device so as to allow fast access speed to the memory device. The sense amplifier includes a first-stage circuit, coupled to the bit lines of the memory device, for amplifying the differential data signal on the bit lines. Furthermore, a second-stage circuit has an input side coupled to receive the output signal from the first-stage circuit and an output side coupled to the bit lines, and is used for amplifying the output signal from the first-stage circuit and feeding the amplified signal back to the bit lines. The first-stage circuit and the second-stage circuit in combination constitute a positive feedback amplification loop coupled to the bit lines for amplifying the differential data signal on the bit lines to a detectable level.

Abstract: The present invention discloses a method of forming a contact window on a substrate. The method in the present invention includes a step of forming a gate structure on said substrate having a gate oxide, a gate electrode on the gate oxide, and a gate electrode protection layer on the gate electrode, a step of forming a protection layer conforming with the substrate and the gate structure, and a step of forming a first insulation layer over the protection layer. The method further includes removing a portion of the first insulation layer and a portion of the protection layer for forming side wall spacers at side walls of the gate structure, performing a ion implantation to the substrate using the gate structure and the side wall spacers as a mask, and then forming a second insulation layer on the substrate, the side wall spacers, and the gate structure.