Abstract: The invention provides a structure of a bonding pad, which comprising: a substrate; a dielectric layer formed over the substrate; a first metal layer formed in the dielectric layer; a second metal layer formed in the dielectric layer and above the first metal layer; a plurality of first plugs formed between the first metal layer and the second metal layer, wherein the plugs are used for connecting the first metal layer with the second metal layer; a third metal layer formed over the dielectric layer; and a plurality of second plugs, formed between the second metal layer and the third metal layer, wherein the second plugs are used for connecting the second metal layer with the third metal layer.

Abstract: A dual damascene structure includes a semiconductor substrate, a metal-oxide-semiconductor (MOS) transistor formed on the substrate and a metal layer. The metal layer is electrically connected to the conducting regions of the MOS transistor through interconnect. The metal layer further includes first metal spacing regions and second metal spacing regions, wherein the width of a first metal spacing region is about 1 to 10 times of the linewidth of the device, and the width of a second spacing region is about 0.8 to 1.2 times of the linewidth of the device. The first metal spacing regions includes a high-permittivity dielectric for a better thermal transferring rate, and the second spacing regions includes a low-permittivity dielectric for a shorter resistance-capacitance delay.

Abstract: An improved dual damascene process is provided. By a spacer formed on sidewalls of an oxide layer, the method can make a via plug and a metal layer serving as an interconnect simultaneously form in a self-aligned process. Therefore, it can successfully avoid misalignment while forming a via plug and an interconnect.

Abstract: A temperature monitor is included inside an ion implanting chamber to constantly monitor the wafer temperature during ion implantation. The measured temperature signal is sent to a central control system through an interface circuit. When an abnormal temperature is detected, the central control system automatically ceases the ion implantation operation and triggers an alarm for operators.

Abstract: A method for forming a SAC opening is provided. As a self-aligned contact (SAC) opening is formed in a dielectric layer on a semiconductor substrate to expose one of source/drain regions in the substrate, a misalignment of the SAC opening may occur to expose a portion of the gate structure. The gate structure has a gate, which is covered by a cap layer on the top, a thin oxide layer on each sidewall of the gate and the cap layer, and a spacer on the thin oxide layer. The SAC opening causes a clearance between the spacer and the gate since a portion of the thin oxide layer is removed. The method contains forming an insulating layer over the substrate to fill the clearance. An etching back process is performed to remove the insulating layer so that a remaining portion of the insulating layer fills the clearance to fully isolate the gate.

Abstract: A method of fabricating a DRAM capacitor. After forming a node contact opening in a dielectric layer on the substrate, a conductive layer having an annulus hollow is formed. A recess is formed on the conductive layer and a spacer is formed on the sidewall of the spacer, after which the annulus hollow is filled with an oxide layer. A photoresist layer for defining the capacitor region is formed. The etching stop layer, the oxide layer, and the spacer are removed to form the bottom electrode. Then, the dielectric layer and the upper electrode are formed in sequence.

Abstract: A method for fabricating a field effect transistor (FET) with a T-like gate structure includes forming a silicon nitride layer over a silicon substrate and patterning it to form an opening that exposes the substrate. A dielectric layer is formed on a lower portion of each side-wall of the opening so that the opening has a T-like free space. A doped polysilicon layer fills the T-like free space through only one deposition. After performing a planarization on the doped polysilicon layer, a titanium metal layer is formed over the substrate. A self-aligned titanium silicide is formed over the substrate other than the dielectric layer surface through a rapid thermal process (RTP). A selective etching process is performed to remove the remaining titanium metal layer. After removing the dielectric layer a RTP is performed again to reform the crystal structure of the titanium silicide layer so as to reduce its resistance. A T-like gate structure is formed.

Abstract: An alignment strategy for asymmetrical alignment marks in a wafer, in which the positions of the a symmetrical alignment marks are determined twice. A first set of positions is detected after a chemical-mechanical polishing step. A second set of positions is detected after a rotation in which the wafer is rotated by 180.degree. in the plane of the surface of the wafer.

Abstract: A photoresist dispense pump receives photoresist from two pipelines, a first pipeline and a second pipeline, and pumps out the photoresist through a third pipeline. The photoresist dispense pump contains a first bellows and a second bellows receiving photoresist from the second pipeline, wherein the first bellows and the second bellows are separated by a partition. Photoresist is fed into the third pipeline from the second bellows. On the center region of the partition, there is a central diaphragm that allows photoresist to flow in a direction from the first bellows toward the second bellows, but not in the reverse direction.

Abstract: A method of improving selectivity between silicon nitride and silicon oxide. A pad oxide is formed on a substrate. Using low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition, a silicon nitride layer is formed on the silicon oxide layer. The silicon nitride is implanted by boron ions to transform into boron nitride. A conventional method is performed to form a shallow trench isolation.

Abstract: A semiconductor fabrication method is provided for fabricating a data-storage capacitor for DRAM (dynamic random-access memory) device, which can allow the resulting capacitor to have a large capacitance and also allows a higher yield rate for the DRAM manufacture process. This method is used on a semiconductor substrate that is already formed with a transfer field effect transistor having a gate and a pair of source/drain regions. By this method, a dielectric layer, an etch-end layer, and an insulating layer are successively formed over the dielectric layer. Then, a contact hole is formed to expose a selected one of the source/drain regions of the transistor. In this contact hole and over the insulating layer, a main conductive trunk is formed, which is substantially T-shaped in cross section, with the root thereof being electrically connected to the source/drain region. Subsequently, an overhanging conductive branch is formed to the main conductive trunk.

Abstract: A method for fabricating a capacitor including a storage capacitor of a dynamic random access memory (DRAM) starts with forming a dielectric layer and then a mask on a provided substrate, wherein the provided substrate contains a pre-formed field effect transistor (FET). By patterning the dielectric layer, a contact window is formed to expose the source/drain regions on the provided substrate. Then, a conducting layer is formed to cover the mask and fill the contact window, wherein the conducting layer is electrically connected to the source/drain region. A hemispherical-grained silicon (HSG) layer is formed on the conducting layer, wherein the silicon grains are respectively surrounded by spacers formed in a follow-up process. The HSG layer and a portion of the conducting layer are removed by performing an anisotropic etching process that uses the spacers as masks. The remains of the conducting layer, a multi-micro-cylinder structure, serves as the storage electrode of a capacitor.

Abstract: A method of fabricating an embedded dynamic random access memory. Using the method of dual damascence, by forming patterning only one dielectric layer, the contact windows with different depth are formed. In addition, the metal layer formed within the metal connecting regions are used as interconnects without further process.

Abstract: An improved aligner detector is provided. The improved aligner detector includes, a detector, several electrooptic modulators, and a refractor set, which includes several wedge patterns. Each of the electrooptic modulators includes a double-refraction transistor, which has a property of double refraction. By applying a special voltage on the double-refraction transistors, the double-refraction transistors can become transparent or opaque. Thereby, the electrooptic modulators can select a desired order of the diffraction light ray. The selected diffraction light ray is refracted by the refractor set to the detector for analysis.

Abstract: A method for forming a shallow trench isolation structure. A mask layer having an opening is formed over a substrate to pattern a shallow trench. A sloped spacer is formed on the sidewalls of the opening. The mask layer and the spacer are used as a hard mask, and a portion of the substrate is removed by anisotropic etching to form a shallow trench isolation structure. The sloped sidewalls of the shallow trench isolation structure and the substrate surface intersect at an obtuse angle. Therefore, the structure prevents stress and avoids leakage current.

Abstract: A method for fabricating a mixed-mode device. A first gate oxide layer and a second gate oxide layer are formed. The polysilicon layer is used as a mask to pattern the gate oxide layers. Additionally, a top electrode is formed during the first gate oxide layer is patterned. A bottom electrode is formed during the second gate oxide layer is patterned. The first gate oxide layer and the second gate oxide layer are formed by a single oxidation operation, thus thicknesses of the first gate oxide layer and the second oxide layer can be effectively controlled.

Abstract: A method of fabricating shallow trench isolation structures. A substrate over which a polysilicon layer and a masking layer are formed is provided. An opening is formed within the polysilicon layer and the masking layer. A trench is then formed within the substrate. An oxide layer is formed within the trench, and the surface of the oxide layer has a same level as the surface of the masking layer. The masking layer is removed and a thermal process is performed to transform the polysilicon layer to a silicon oxide layer. The silicon oxide layer is removed by an wet etching process and a shallow trench isolation structure is accomplished.

Abstract: A circuit structure which avoids a latchup effect. An N-well is formed in a P-type substrate. An N-type contact is formed in the N-well. A PMOS is located on the N-well. A gate of the PMOS connects to an input terminal and a source region of the PMOS connects to a voltage source. A first NMOS and a second NMOS are located on the P-type substrate. A gate of the first NMOS connects to the input terminal, a source region of the first NMOS connects to a ground terminal, and a drain region of the first NMOS connects to an output terminal and a drain region of the PMOS. A gate of the second NMOS connects to the output terminal, a source region of the second NMOS connects to a voltage source, and a drain region of the second NMOS connects to the N-type contact.

Abstract: A decoding method is used for a ROM matrix having silicon controlled rectifier memory units. In the memory units a voltage is applied to the emitter terminal and the base terminal of the first transistor of a silicon controlled rectifier unit so that the silicon controlled rectifier memory unit is operational. Current flows via the emitter terminal of the second transistor of the silicon controlled rectifier unit to the common electrode and can be detected. Decoding comprises selecting a memory unit for a read operation by applying a first voltage to the triggering word line electrode, that is electrically coupled to the selected memory unit, while applying a second voltage which is bigger than the first voltage to the remaining triggering word line electrodes.