Abstract: A jig and a method for grinding probe pins of a probe card. The jig includes a carrier and a connecting part. The carrier carries a support body with a grinding sheet, and the carrier includes an opening. The support body with the grinding sheet straddles above the opening. The opening may expose a plurality of probe pins of the probe card.

Abstract: According to an exemplary embodiment, the disclosure provides a memory device which includes but not limited to a memory array including a plurality of memory cells, a first terminal of each of the plurality of memory cells is connected to a bit line, a second terminal of each of the plurality of memory cells is connected to a source line, and a third terminal of each of the plurality of memory cells is connected to a word line, wherein the word line is associated with a word line address, and a resistance trimming circuit connected to either the source line, the bit line or a common source line and configured to receive a trimming code to change an equivalent resistance of the source line or the bit line based on the trimming code, wherein the trimming code is tied to the word line address.

Abstract: A semiconductor device includes a substrate, a high-Q capacitor, an ultra high density capacitor, and an interconnection. At least one trench is formed in the substrate. The high-Q capacitor is disposed on a surface of the substrate, and includes a bottom electrode, an upper electrode located on the bottom electrode, and a first dielectric layer located between the upper and bottom electrodes. The ultra high density capacitor is disposed on the trench of the substrate, and includes a first electrode conformally deposited in the trench, a second electrode located on the first electrode, and a second dielectric layer located between the first and second electrodes. The interconnection connects one of the upper electrode and the bottom electrode to one of the first electrode and the second electrode, and connects the other of the upper electrode and the bottom electrode to the other of the first electrode and the second electrode.

Abstract: According to an aspect of the disclosure, the disclosure provides an ADC which includes not limited to: a DAC configured to generate a positive input delta voltage and a negative input delta voltage, a comparator electrically connected to the DAC and configured to receive the positive input delta voltage to generate a first digital output value and to receive the negative input delta voltage to generate a second digital output value, a logic circuit configured to receive, from the comparator, the first digital output value and the second digital output value to generate a digital quantization code according to half of a sum of the first digital output value and the second digital output value, and a calibration circuit configured to receive the digital quantization code from the logic circuit and calibrate an output of the ADC according to the digital quantization code to eliminate an offset error value.

Abstract: A calabash-shaped MIM capacitor structure includes a stacked layer. The stacked layer includes numerous dielectric layers. An MIM capacitor is disposed within the stacked layer. The MIM capacitor includes a calabash-shaped profile. The calabash-shaped profile includes a rounded bottom, a narrow body and a rounded shoulder disposed from bottom to top.

Abstract: A semiconductor device including a substrate, a fin, a gate structure, a single diffusion break (SDB) structure and a capacitor gate structure. The substrate has a first region and a second region, wherein the second region is located between the adjacent first regions. The fin is disposed on the substrate, wherein the fin located in the second region includes a heavily doped region. The gate structure is disposed on the fin and located in the first region. The SDB structure is disposed on the fin and located in the second region. The capacitor gate structure is disposed on the fin and is located in the second region, wherein the capacitor gate structure is disposed on the SDB structure. A manufacturing method of a semiconductor device is also provided.

Abstract: A semiconductor structure including a first substrate, a first conductive layer, and first bonding pads is provided. The first conductive layer is located on the first substrate. The first conductive layer includes a main body portion and an extension portion. The extension portion is connected to the main body portion and includes a terminal portion away from the main body portion. The first bonding pads are connected to the main body portion and the extension portion. The number of the first bonding pads connected to the terminal portion of the extension portion is plural.

Abstract: A capacitance measurement method for a capacitive device is provided. The method includes: providing a wafter, on which the capacitive device is formed, having a set of calibration test pads and a set of test pads; applying a test signal to the set of calibration test pads through a first test path to measure a first capacitance between two calibration test pads; applying the test signal to the set of test pads through a second test path to measure a second capacitance between two test pads; and obtaining a capacitance of the capacitive device by a difference between the first capacitance and the second capacitance.

Abstract: Disclosed is a capacitor structure including a substrate, a stack structure, and a capacitor. The stack structure includes at least one first dielectric layer and at least one second dielectric layer alternately disposed on the substrate. There is a trench in the at least one first dielectric layer, the at least one second dielectric layer, and the substrate. The trench has at least one recess on at least one sidewall of the at least one first dielectric layer. The capacitor is disposed on a surface of the trench.

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the HEMT device are provided. The HEMT device includes a substrate, a channel layer, a barrier layer, and a gate structure. The substrate has at least one active region. The channel layer is disposed on the at least one active region. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The gate structure includes a metal layer and a P-type group III-V semiconductor layer vertically disposed between the metal layer and the barrier layer. The P-type group III-V semiconductor layer includes a lower portion and an upper portion on the lower portion, and the upper portion has a top area greater than a top area of the lower portion.

Abstract: A high electron mobility transistor includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a dielectric layer on the barrier layer, a gate structure on the dielectric layer, and a source electrode and a drain electrode on the dielectric layer at two sides of the gate structure. The source electrode and the drain electrode respectively include a body portion and a plurality of protruding portions. A bottom surface of the body portion directly contacts a top surface of the dielectric layer. The protruding portions are connected to the bottom surface of the body portion and penetrate through the dielectric layer the barrier layer and a portion of the channel layer.

Abstract: A fully-isolated metal oxide semiconductor (MOS) device includes a substrate, an isolation well, a gate structure, a source region, a gradient region, a drain region, a first well, and an electro static discharge (ESD) protection region. The isolation well is formed in the substrate, and the gate structure is formed on the isolation well. The source region and the gradient region are formed in the isolation wells on both sides of the gate structure respectively, and the drain region is formed in the gradient region. The first well is formed below the drain region in the gradient region, and the ESD protection region is formed in the first well. The isolation well and the ESD protection region have a first conductivity type, and the gradient region and the first well have a second conductivity type.

Abstract: The invention provides a semiconductor structure, which comprises a substrate, a high-voltage device region is defined on the substrate, in the high-voltage device region, the substrate comprises a first region, a first groove surrounds the first region, and a second region surrounds the first groove, and a contact gate structure is located in the high-voltage device region, when viewed from a top view, the contact gate structure comprises a plurality of columnar dielectric layers arranged in an array.

Abstract: A method for manufacturing an integrated circuit device includes the following steps. A first gate structure of a medium voltage device (MVP) having a first conductivity type and a second gate structure of a high voltage device (HVP) having the first conductivity type, a third gate structure of a medium voltage device (MVN) having a second conductivity type, and a fourth gate structure of a high voltage device (HVN) having the second conductivity type are respectively formed in first to fourth regions of a substrate. First lightly doped drain regions (PLDD) having the first conductivity type are formed in the substrate respectively in the first, second and fourth regions aside the first, second and fourth gate structures. Second lightly doped drain regions (NLDD) having the second conductivity type are formed in the substrate respectively in the third and fourth regions aside the third and fourth gate structures.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

Abstract: Provided is a resistive memory structure and a manufacturing method thereof. The resistive memory structure includes a substrate, a dielectric layer, a resistive memory device, a hard mask layer, and a spacer. The dielectric layer is located on the substrate. The dielectric layer has an opening. The resistive memory device is located in the opening and has a protrusion outside the opening. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The hard mask layer covers a top surface of the variable resistance layer. The spacer covers a sidewall of the variable resistance layer in the protrusion.

Abstract: Provided are a multiple-level interconnect structure having a scatterometry test layer and a manufacturing method thereof. The multiple level interconnect structure includes a patterned reflective layer, a bulk reflective layer and a patterned test layer. The patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern separated from each other. The bulk reflective layer is disposed on the patterned reflective layer. The patterned test layer is disposed on the bulk reflective layer.

Abstract: A semiconductor device includes a substrate, a high-Q capacitor, an ultra high density capacitor, and an interconnection. At least one trench is formed in the substrate. The high-Q capacitor is disposed on a surface of the substrate, and includes a bottom electrode, an upper electrode located on the bottom electrode, and a first dielectric layer located between the upper and bottom electrodes. The ultra high density capacitor is disposed on the trench of the substrate, and includes a first electrode conformally deposited in the trench, a second electrode located on the first electrode, and a second dielectric layer located between the first and second electrodes. The interconnection connects one of the upper electrode and the bottom electrode to one of the first electrode and the second electrode, and connects the other of the upper electrode and the bottom electrode to the other of the first electrode and the second electrode.

Abstract: The invention provides a semiconductor layout pattern, which comprises a substrate, a plurality of gate metal frames arranged on the substrate, a plurality of source/drain patterns and a plurality of gate patterns extending along an X direction and located in each gate metal frame, and the source/drain patterns and the plurality of gate patterns are alternately arranged along a Y direction, wherein any two adjacent gate metal frames are partially overlapped with each other, and the overlapping part of the two gate metal frames is defined as an overlapping line.

Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, a seal ring structure including first and second interconnect structures, and a passivation layer on the seal ring structure and the second dielectric layer. The first interconnect structure is located in the first dielectric layer. The second interconnect structure is located in the second dielectric layer and connected to the first interconnect structure. The passivation layer has a spacer portion covering a sidewall of the second dielectric layer and a portion of the first dielectric layer. A ditch exists in the passivation layer and the first dielectric layer. The spacer portion is located between the ditch and the seal ring structure. The semiconductor structure is able to reduce time and power of an etching process for forming the ditch.