Abstract: Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate having a first memory region. The first memory region includes a first dielectric layer, a first floating gate, a first inter-gate dielectric layer, a control gate and a first contact. The first dielectric layer is disposed on the substrate. The first floating gate is disposed on the first dielectric layer. The first inter-gate dielectric layer is disposed on the first floating layer. The control gate is disposed on the first inter-gate dielectric layer. The first contact penetrates through the first control gate and the first inter-gate dielectric layer and is landed on the first floating gate.

Abstract: A semiconductor device includes a III-V compound semiconductor layer and a source/drain structure. The source/drain structure is disposed on the III-V compound semiconductor layer. The source/drain structure includes a metal layer and metal silicide patterns. The metal layer is disposed on the metal silicide patterns, and a portion of the metal layer is disposed between the metal silicide patterns adjacent to each other.

Abstract: A dissection method for optical proximity correction includes the following steps. An initial dissection is performed to define each side of a layout pattern as an original segment so as to form multiple original segments. It is determined whether an opposite side of a target side has an inside corner. A corner opposite dissection is performed to a target side to form multiple intermediate segments. It is judge which type of included angles between a target segment and each of its adjacent sides belongs to. A symmetrical dissection is performed according to the type of the included angles.

Abstract: Provided is a semiconductor including a substrate, a semiconductor element disposed on the substrate, an interconnect structure, first and second power deliver lines, and first and second power deliver network (PDN) structures. The interconnect structure is disposed in the element region, above the semiconductor element, and electrically connected with the semiconductor element. The first and the second power deliver lines are disposed above the interconnect structure and electrically connected to the first and the second power supplies, respectively. The first PDN structure is disposed between the substrate and the first power deliver line, and connected to the first power deliver line and a lowest circuit layer of the interconnect structure. The second PDN structure is disposed between the substrate and the second power deliver line, and connected to the second power deliver line and the lowest circuit layer of the interconnect structure.

Abstract: A photomask structure including a layout pattern, a first L-type assist pattern, and a second L-type assist pattern is provided. An end portion of the layout pattern includes a first edge, a second edge, and a third edge. The second edge is connected to one end of the first edge, and the third edge is connected to another end of the first edge. The first L-type assist pattern is located between the second L-type assist pattern and the first edge. The layout pattern, the first L-type assist pattern, and the second L-type assist pattern are separated from each other. The first L-type assist pattern surrounds the first edge and the second edge. The second L-type assist pattern surrounds the first edge and the third edge.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor channel layer, a second semiconductor channel layer, and an isolation structure. The first semiconductor channel layer, the second semiconductor channel layer, and the isolation structure are disposed above the semiconductor substrate. The isolation structure includes a vertical portion, a first horizontal portion, and a second horizontal portion. The vertical portion is disposed between the first semiconductor channel layer and the second semiconductor channel layer in a horizontal direction. The first horizontal portion is disposed between the first semiconductor channel layer and the semiconductor substrate in a vertical direction. The second horizontal portion is disposed between the second semiconductor channel layer and the semiconductor substrate in the vertical direction. The first horizontal portion and the second horizontal portion are connected with the vertical portion.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a patterned mask on the buffer layer, using the patterned mask to remove the buffer layer for forming ridges and a damaged layer on the ridges; removing the damaged layer, forming a barrier layer on the ridges; and forming a p-type semiconductor layer on the barrier layer.

Abstract: A probe card is provided. The probe card includes a circuit board, a base board and a plurality of probing tips. The base board is disposed on the circuit board, wherein the base board includes at least three probe regions respectively disposed at at least three corners of the base board. The plurality of probing tips are disposed on the base board and electrically connected with the circuit board.

Abstract: A semiconductor device is provided. The semiconductor device includes a device substrate, having a device structure layer and a buried dielectric layer, wherein the buried dielectric layer is disposed on a semiconductor layer of the device structure layer and the device substrate comprises a device structure. A metal layer is disposed on the buried dielectric layer and surrounded by a first inter-layer dielectric (ILD) layer. A region of the metal layer has a plurality of openings. The buried dielectric layer has an air gap under and exposing the region of the metal layer with the openings, wherein the air gap is located above the device structure in the device substrate. A second ILD layer is disposed on the metal layer and sealing the air gap at the openings of the metal layer.

Abstract: A method for forming a semiconductor memory device is disclosed. A substrate is provided. A pair of floating gates are formed on the substrate. A recessed region is formed in the substrate between the floating gates, wherein an upper surface of the recessed region has a concave profile lower than a surface of the substrate and with a radius between 40 nm and 60 nm in a cross-sectional view perpendicular to the floating gates. A source line doped region is formed in the recessed region. An erase gate is formed between the floating gates and on the recessed region, and a word line is formed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate. A bit line doped region is formed in the substrate and adjacent to the word line.

Abstract: A semiconductor structure includes following components. A first substrate has a first surface and a second surface opposite to each other. An HBT device is located on the first substrate and includes a collector, a base, and an emitter. A first interconnect structure is electrically connected to the base, located on the first surface, and extends to the second surface. A second interconnect structure is electrically connected to the emitter, located on the first surface, and extends to the second surface. A third interconnect structure is located on the second surface and electrically connected to the collector. An MOS transistor device is located on a second substrate and includes a gate, a first source and drain region, and a second source and drain region. Interconnect structures on the second substrate electrically connect the base to the first source and drain region and electrically connect the emitter to the gate.

Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

Abstract: A semiconductor device includes a substrate, a doped ring, a plurality of contacts, and a plurality of conductive lines. The substrate includes a first region and a second region surrounding the first region. The doped ring is located in the substrate in the second region and surrounds the first region. The doped ring includes a first doped region and a plurality of second doped regions. The first doped region is located in the substrate in the second region and surrounds the first region. The first doped region has an opening. The second doped regions are separated from each other and located in the substrate of the opening. The contacts are electrically connected to the second doped regions. The conductive lines are connected to the contacts and a plurality of conductive layers in the first region.

Abstract: A lithography system includes an immersion lithographic apparatus, a fluid supply device, and a sensor. The fluid supply is configured to supply fluid to the immersion lithographic apparatus. The fluid supply device includes at least one liquid storage tank, an upper liquid pipe and a lower liquid pipe connected to the liquid storage tank. The sensor includes at least one hydraulic pressure gauge. The at least one hydraulic pressure gauge is arranged near a lower part of the liquid storage tank and connected to the lower liquid pipe and the upper liquid pipe so as to measure the hydraulic pressure at a bottom of the liquid storage tank. The height of the liquid level in the liquid storage tank is calculated from the hydraulic pressure.

Abstract: Provided are a power MOSFET and a manufacturing method thereof. The power MOSFET includes a substrate, base, doped and drift regions, a gate structure, an insulating layer, a conductive layer, a source electrode and a drain electrode. The base region is in the substrate and adjacent to a first surface of the substrate. The doped region is in the base region and adjacent to the first surface. The drift region is under the base region. The gate structure is in the substrate and includes first and second portions. The first portion is located in the drift region. The second portion is located in the doping, base and drift regions. The insulating layer is disposed between the gate structure and the substrate. The conductive layer surrounds the second portion. The source electrode is connected to the doped region. The drain electrode is disposed on a second surface of the substrate.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Abstract: A high electron mobility transistor (HEMT) device including a substrate, a channel layer, a barrier layer, a p-type gallium nitride (GaN) spacer, a gate electrode, a source electrode, and a drain electrode is provided. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer and has a protruding portion. The P-type GaN spacer is disposed on a side wall of the protruding portion. The gate electrode is disposed on the protruding portion and the P-type GaN spacer. The source electrode and the drain electrode are disposed on two sides of the gate electrode.

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.