Patents Assigned to United Microelectronics Corp.
  • Method for forming semiconductor device
    Patent number: 11876122
    Abstract: A method of forming a semiconductor device. A substrate having a fin structure is provided. A dummy gate is formed on the fin structure. A polymer block is formed adjacent to a corner between the dummy gate and the fin structure. The polymer block is subjected to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block. After subjecting the polymer block to the nitrogen plasma treatment, a seal layer is formed on the sidewall of the dummy gate and on the polymer block. An epitaxial layer is then grown on a source/drain region of the fin structure. The dummy gate is then replaced with a metal gate.
    Type: Grant
    Filed: November 27, 2022
    Date of Patent: January 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wei Chang, Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Shao-Wei Wang, Yu-Ren Wang, Chia-Yuan Chang
  • Magnetoresistive random access memory having a ring of magnetic tunneling junction region surrounding an array region
    Patent number: 11877520
    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
    Type: Grant
    Filed: February 9, 2023
    Date of Patent: January 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
  • Method for enlarging tip portion of a fin-shaped structure
    Patent number: 11876095
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: January 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • Semiconductor structure and manufacturing method thereof
    Publication number: 20240014082
    Abstract: The invention provides a semiconductor structure, which comprises a chip comprising a substrate, wherein the substrate has a front surface and a back surface, and the front surface of the substrate comprises a circuit layer, the back surface of the substrate comprises a plurality of microstructures, and a thermal interface material located on the back surface of the substrate, and the thermal interface material contacts the microstructures directly.
    Type: Application
    Filed: August 18, 2022
    Publication date: January 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Yi-Feng Hsu
  • MAGNETIC MEMORY AND MANUFACTURING METHOD THEREOF
    Publication number: 20240016067
    Abstract: A magnetic memory including a substrate, a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ) stack, a first protection layer, and a second protection layer is provided. The SOT layer is located over the substrate. The MTJ stack is located on the SOT layer. The first protection layer and the second protection layer are located on the sidewall of the MTJ stack. The first protection layer is located between the second protection layer and the MTJ stack. There is a notch between the second protection layer and the SOT layer.
    Type: Application
    Filed: August 10, 2022
    Publication date: January 11, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chih-Wei Kuo, Chung Yi Chiu, Yi-Wei Tseng, Hsuan-Hsu Chen, Chun-Lung Chen
  • METHOD OF FABRICATING MAGNETIC TUNNELING JUNCTION DEVICE
    Publication number: 20240016062
    Abstract: A method of fabricating an MTJ device is provided including the following process. A first via is formed in the first dielectric layer. A first electrode layer is formed on the first dielectric layer and the first via. An MTJ stack layer is formed on the first electrode layer. A patterned second electrode layer is formed on the MTJ stack layer and used as a mask. A first ion beam etching process is performed to etch the patterned second electrode layer and pattern the MTJ stack layer and the first electrode layer to form a second electrode, an MTJ stack structure, and a first electrode. A first protective layer is formed to cover the second electrode and the MTJ stack structure. A second ion beam etching process is performed to remove a portion of the MTJ stack structure and a portion of the first electrode.
    Type: Application
    Filed: July 27, 2022
    Publication date: January 11, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Shun-Yu Huang, Yi-Wei Tseng, Chih-Wei Kuo, Yi-Xiang Chen, Hsuan-Hsu Chen, Chun-Lung Chen
  • PHOTOMASK STRUCTURE
    Publication number: 20240012322
    Abstract: A photomask structure including a layout pattern and at least one assist pattern is provided. The layout pattern includes corners. The assist pattern wraps at least one of the corners. There is a gap between the edge of the layout pattern and the assist pattern.
    Type: Application
    Filed: July 31, 2022
    Publication date: January 11, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Chen Sun, Song-Yi Lin, En-Chiuan Liou
  • ONE-TIME PROGRAMMABLE MEMORY STRUCTURE
    Publication number: 20240015958
    Abstract: A one-time programmable memory structure comprises: A transistor includes a gate. A capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is disposed on the first electrode. A top surface of the first electrode and a top surface of the gate are located on a same plane perpendicular to a direction of the first electrode toward the second electrode. An interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode. A resistor comprises a conductive layer. Top and bottom surfaces of the conductive layer are respectively located on a same plane, perpendicular to the direction of the first electrode toward the second electrode, with the top and bottom surfaces of the gate.
    Type: Application
    Filed: September 20, 2023
    Publication date: January 11, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Kuo-Hsing Lee, Chi-Horn Pai, Chang Chien Wong, Sheng-Yuan Hsueh, Ching Hsiang Tseng, Shih-Chieh Hsu
  • MRAM STRUCTURE AND METHOD OF FABRICATING THE SAME
    Publication number: 20240016063
    Abstract: An MRAM structure includes an MTJ, a first SOT element, a conductive layer and a second SOT element disposed from bottom to top. A protective layer is disposed on the second SOT element. The protective layer covers and contacts a top surface of the second SOT element. The protective layer is an insulator. A conductive via penetrates the protective layer and contacts the second SOT element.
    Type: Application
    Filed: August 9, 2022
    Publication date: January 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Chung-Yi Chiu, Shun-Yu Huang, Yi-Wei Tseng
  • COPPER PILLAR BUMP STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240014158
    Abstract: A copper pillar bump (CPB) structure is provided in the present invention, including a substrate, a pad on the substrate, a passivation layer covering the substrate and exposing the pad, and a copper pillar on the passivation layer and the pad and connecting directly with the pad. The copper pillar is provided with an upper part and a lower part, and a top surface of the lower part includes a first top surface and a second top surface. The second top surface is on one side of the first top surface, and the upper part of the copper pillar is on the first top surface of the lower part. A metal bump is on the copper pillar, wherein parts of the metal bump directly contact the second top surface of the lower part.
    Type: Application
    Filed: August 29, 2022
    Publication date: January 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Hsiao Wang, Kai-Kuang Ho
  • METAL INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20240014069
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.
    Type: Application
    Filed: September 26, 2023
    Publication date: January 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai
  • HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FABRICATING THE SAME
    Publication number: 20240014309
    Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer, wherein the composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode and a drain electrode are disposed on the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer between the source electrode and the drain electrode. An insulating layer is disposed between the drain electrode and the gate electrode and covering the second III-V compound layer. Numerous electrodes are disposed on the insulating layer and contact the insulating layer, wherein the electrodes are positioned between the gate electrode and the drain electrode and a distribution of the electrodes decreases along a direction toward the gate electrode.
    Type: Application
    Filed: September 20, 2023
    Publication date: January 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Chih-Tung Yeh
  • Semiconductor Structure with Features of D-mode and E-mode GaN Devices and Semiconductor Process Thereof
    Publication number: 20240014306
    Abstract: A semiconductor device provided with features of depletion mode (D-mode) and enhancement mode (E-mode) GaN devices, including a substrate with a first region and a second region defined thereon, a GaN channel layer on the substrate, a AlGaN layer on the GaN channel layer, a p-GaN layer on the AlGaN layer in the first region, a Al-based passivation layer on the AlGaN layer and p-GaN layer, and gate contact openings, wherein the gate contact opening on the first region extends through the Al-based passivation layer to the top surface of p-GaN layer, the gate contact opening on the second region extends through the Al-based passivation layer to the surface of AlGaN layer, and the surfaces of p-GaN layer and AlGaN layer are both flat surfaces without recess feature.
    Type: Application
    Filed: August 12, 2022
    Publication date: January 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, Ruey-Chyr Lee, Wen-Jung Liao
  • SEMICONDUCTOR DEVICE
    Publication number: 20240014311
    Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer and a recess. The group III-V body layer is disposed on the substrate. The group III-V barrier layer is disposed on the group III-V body layer in the active region and the isolation region. The recess is disposed in the group III-V barrier layer without penetrating the group III-V barrier layer in the active region.
    Type: Application
    Filed: September 26, 2023
    Publication date: January 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Wen-Jung Liao
  • HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME
    Publication number: 20240014310
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.
    Type: Application
    Filed: September 21, 2023
    Publication date: January 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20240014307
    Abstract: A high electron mobility transistor (HEMT) device and a method of forming the HEMT device are provided. The HEMT device includes a substrate, a channel layer, a barrier layer, and a gate structure. The substrate has at least one active region. The channel layer is disposed on the at least one active region. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The gate structure includes a metal layer and a P-type group III-V semiconductor layer vertically disposed between the metal layer and the barrier layer. The P-type group III-V semiconductor layer includes a lower portion and an upper portion on the lower portion, and the upper portion has a top area greater than a top area of the lower portion.
    Type: Application
    Filed: August 16, 2022
    Publication date: January 11, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Wei Jen Chen, Kai Lin Lee
  • Resistive random-access memory (RRAM) device and forming method thereof
    Patent number: 11871685
    Abstract: A RRAM device includes a bottom electrode, a resistive material layer, a high work function layer, a top electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the high work function layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming said RRAM device is also provided.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: January 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Semiconductor device comprising magnetic tunneling junctions (MTJs) in a magnetoresistive random access memory (MRAM)
    Patent number: 11871585
    Abstract: A semiconductor device includes a sense amplifier, a first magnetic tunneling junction (MTJ) connected to the sense amplifier at a first distance, a second MTJ connected to the sense amplifier at a second distance, and a third MTJ connected to the sense amplifier at a third distance. Preferably, the first distance is less than the second distance, the second distance is less than the third distance, a critical dimension of the first MTJ is less than a critical dimension of the second MTJ, and the critical dimension of the second MTJ is less than a critical dimension of the third MTJ.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: January 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wei Wang, Yi-An Shih, Huan-Chi Ma
  • High voltage transistor device and method for fabricating the same
    Patent number: 11869953
    Abstract: A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: January 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP
    Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
  • Method for fabricating semiconductor device
    Patent number: 11871677
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: January 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai, Da-Jun Lin, Chau-Chung Hou, Wei-Xin Gao