Patents Assigned to United Microelectronics Corps.
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Publication number: 20240162401Abstract: A method for fabricating a micro display device includes the steps of providing a wafer comprising a first area, a second area, and a third area, forming first bonding pads on the first area, forming second bonding pads on the second area, and forming third bonding pads on the third area. Preferably, the first bonding pads and the second bonding pads are made of different materials and the first bonding pads and the third bonding pads are made of different materials.Type: ApplicationFiled: December 9, 2022Publication date: May 16, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chun-Ting Yeh
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Publication number: 20240162208Abstract: A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.Type: ApplicationFiled: December 7, 2022Publication date: May 16, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Chih-Wei Chang, Fu-Yu Tsai, Bin-Siang Tsai, Chung-Yi Chiu
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Publication number: 20240162220Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.Type: ApplicationFiled: December 8, 2022Publication date: May 16, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Yu Chen, Chun-Hao Lin, Yuan-Ting Chuang, Shou-Wei Hsieh
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Publication number: 20240162038Abstract: A photomask structure including a first layout pattern and a second layout pattern is provided. The second layout pattern is located on one side of the first layout pattern. The first layout pattern and the second layout pattern are separated from each other. The first layout pattern has a first edge and a second edge opposite to each other. The second layout pattern has a third edge and a fourth edge opposite to each other. The third edge of the second layout pattern is adjacent to the first edge of the first layout pattern. The second layout pattern includes a first extension portion exceeding an end of the first layout pattern. The first extension portion includes a first protruding portion protruding from the third edge of the second layout pattern. The first protruding portion exceeds the first edge of the first layout pattern.Type: ApplicationFiled: February 10, 2023Publication date: May 16, 2024Applicant: United Microelectronics Corp.Inventors: Chien Heng Liu, Chia-Wei Huang, Yung-Feng Cheng, Ming-Jui Chen
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Publication number: 20240161818Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.Type: ApplicationFiled: November 30, 2022Publication date: May 16, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Li-Ping Huang, Yu-Fang Chen, Chun-Yen Tseng, Tzu-Feng Chang, Chun-Chieh Chang
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Publication number: 20240162093Abstract: A method for fabricating semiconductor device includes first providing a substrate having a core region, a LNA region, a I/O region, and a PA region, forming a first gate structure on the LNA region, a second gate structure on the PA region, a third gate structure on the core region, and a fourth gate structure on the I/O region, forming an interlayer dielectric (ILD) layer on the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure, and then forming a first hard mask on the first gate structure and a second hard mask on the second gate structure. Preferably, a width of the first hard mask is greater than a width of the first gate structure.Type: ApplicationFiled: December 13, 2022Publication date: May 16, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chu-Chun Chang, Purakh Raj Verma, Chia-Huei Lin, Kuo-Yuh Yang
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Publication number: 20240162218Abstract: An electrostatic discharge device including a gate structure, a plurality of first doped regions, and a plurality of second doped regions. The gate structure is disposed on a substrate. The gate structure includes a body part and a plurality of extension parts. The extension parts are connected with the body part, and an extension direction of the body part is different from an extension direction of the extension parts. The first doped regions are located in the substrate between the extension parts. The second doped regions are located in the substrate at two outer sides of the extension parts. The first doped regions and the second doped regions have different conductivity types.Type: ApplicationFiled: February 6, 2023Publication date: May 16, 2024Applicant: United Microelectronics Corp.Inventors: Chih Hsiang Chang, Mei-Ling Chao, Yin-Chia Tsai, Tien-Hao Tang, Kuan-Cheng Su
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Publication number: 20240162313Abstract: A method for forming a high electron mobility transistor is disclosed. A mesa structure having a channel layer and a barrier layer is formed on a substrate. The mesa structure has two first edges extending along a first direction and two second edges extending along a second direction. A passivation layer is formed on the substrate and the mesa structure. A first opening and a plurality of second openings connected to a bottom surface of the first opening are formed and through the passivation layer, the barrier layer and a portion of the channel layer. In a top view, the first opening exposes the two first edges of the mesa structure without exposing the two second edges of the mesa structure. A metal layer is formed in the first opening and the second openings thereby forming a contact structure.Type: ApplicationFiled: January 18, 2024Publication date: May 16, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Tung Yeh, Chun-Liang Hou, Wen-Jung Liao, Chun-Ming Chang, Yi-Shan Hsu, Ruey-Chyr Lee
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Publication number: 20240162291Abstract: A transistor with a fin structure and a nanosheet includes a fin structure. A first gate device is disposed on the fin structure. A first source/drain layer is disposed at one side of the first gate device. A first source/drain layer is on the fin structure and extends into the fin structure. A second source/drain layer is disposed at another side of the first gate device. The second source/drain layer is on the fin structure and extends into the fin structure. A nanosheet is disposed above the first gate device, between the first source/drain layer and the second source/drain layer, and contacts the first source/drain layer and the second source/drain layer. A second gate device surrounds the nanosheet.Type: ApplicationFiled: December 7, 2022Publication date: May 16, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-In Wu, Yu-Ming Lin, Cheng-Tung Huang
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Patent number: 11984442Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.Type: GrantFiled: April 8, 2022Date of Patent: May 14, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ruei-Yau Chen, Wei-Jen Wang, Kun-Yuan Wu, Chien-Fu Chen, Chen-Hsien Hsu
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Publication number: 20240154027Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.Type: ApplicationFiled: January 16, 2024Publication date: May 9, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Han Wu, Kai-Kuen Chang, Ping-Hung Chiang
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Publication number: 20240154512Abstract: A current generator includes a startup circuit and a bandgap reference circuit coupled to the startup circuit. The startup circuit is for generating a first voltage. The bandgap reference circuit is for generating a second voltage. The bandgap reference circuit includes an operational amplifier. The operational amplifier includes a bias source circuit and a bias generator circuit. The bias source circuit is for generating a reference current according to the first voltage and the second voltage. The bias generator circuit is for generating bias voltages according to the reference current. The startup circuit and the bandgap reference circuit receive a supply voltage.Type: ApplicationFiled: December 15, 2022Publication date: May 9, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsiu-Ming Yeh, Min-Chia Wang
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Publication number: 20240153812Abstract: A method for fabricating a semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a first gate structure on the substrate and adjacent to the STI, forming a first doped region between the first gate structure and the STI, forming a second doped region between the first doped region and the first gate structure, forming a first contact plug on the first doped region, and then forming a second contact plug on the second doped region.Type: ApplicationFiled: December 4, 2022Publication date: May 9, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wen-Kai Lin, Chi-Horn Pai, Sheng-Yuan Hsueh, Kuo-Hsing Lee, Chih-Kai Kang
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Publication number: 20240155843Abstract: A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.Type: ApplicationFiled: November 28, 2022Publication date: May 9, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wang Xiang, CHIA CHING HSU, Shen-De Wang, Yung-Lin Tseng, WEICHANG LIU
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Patent number: 11977335Abstract: A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.Type: GrantFiled: June 21, 2021Date of Patent: May 7, 2024Assignee: United Microelectronics Corp.Inventors: Min Cheng Yang, Wei Cyuan Lo, Yung-Feng Cheng
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Patent number: 11977367Abstract: A command script editing method, a command script editor and a graphic user interface are provided. The command script editing method includes the following steps. The command node is edited according to at least one inputting action or at least one image identifying action performed on the operation frame when the command script editor is at an image editing mode. The command node is edited according to a setting content of at least one process action when the command script editor is at a process editing mode.Type: GrantFiled: May 12, 2021Date of Patent: May 7, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Chi Lin, Li-Hsin Yang, Yu-Shan Hsu
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Publication number: 20240145564Abstract: The invention provides a semiconductor structure, which comprises a substrate, a gate dielectric layer on the substrate, wherein the gate dielectric layer comprises two sidewall portions and a horizontal portion between the two sidewall portions, wherein a height of the horizontal portion is lower than that of the two sidewall portions, and the horizontal portion and the two sidewall portions are perpendicular to each other, and a gate conductive layer on the horizontal portion of the gate dielectric layer.Type: ApplicationFiled: November 25, 2022Publication date: May 2, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Tzu-I Tsai, Shih-An Huang
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Publication number: 20240145412Abstract: A semiconductor device includes a logic circuit region having at least one core device and at least one input/output (I/O) device. The at least one core device has a first accumulative antenna ratio, and the at least one I/O device has a second accumulative antenna ratio. The first accumulative antenna ratio is greater than the second accumulative antenna ratio.Type: ApplicationFiled: November 27, 2022Publication date: May 2, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shih-Che Huang, Chao-Ting Chen, Jui-Fa Lu, Chi-Heng Lin
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Publication number: 20240144994Abstract: A random access memory, including a write transistor with a gate electrically connected to a write word line and a drain electrically connected to a write bit line, a first read transistor and a second read transistor with gates electrically connected to a source of the write transistor to form a storage node, drains electrically connected to a read bit line and a common source electrically connected to a read word line so that the first read transistor and a second read transistor are in parallel connection, and a capacitor electrically connected to the storage node.Type: ApplicationFiled: November 29, 2022Publication date: May 2, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ming-Hsiu Wu, Tsung-Hsun Wu
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Publication number: 20240145594Abstract: A method for fabricating semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a gate structure on the STI and the substrate, forming a patterned mask on the STI and the gate structure, performing an etching process to remove part of the STI for forming a first trench adjacent to one side of the gate structure and a second trench adjacent to another side of the gate structure, and then forming a contact etch stop layer (CESL) on the gate structure and into the first trench and the second trench.Type: ApplicationFiled: November 24, 2022Publication date: May 2, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventor: Po-Yu Yang