Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.

Abstract: An electrostatic discharge device including a gate structure, a plurality of first doped regions, and a plurality of second doped regions. The gate structure is disposed on a substrate. The gate structure includes a body part and a plurality of extension parts. The extension parts are connected with the body part, and an extension direction of the body part is different from an extension direction of the extension parts. The first doped regions are located in the substrate between the extension parts. The second doped regions are located in the substrate at two outer sides of the extension parts. The first doped regions and the second doped regions have different conductivity types.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: A method for fabricating a micro display device includes the steps of providing a wafer comprising a first area, a second area, and a third area, forming first bonding pads on the first area, forming second bonding pads on the second area, and forming third bonding pads on the third area. Preferably, the first bonding pads and the second bonding pads are made of different materials and the first bonding pads and the third bonding pads are made of different materials.

Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.

Abstract: A current generator includes a startup circuit and a bandgap reference circuit coupled to the startup circuit. The startup circuit is for generating a first voltage. The bandgap reference circuit is for generating a second voltage. The bandgap reference circuit includes an operational amplifier. The operational amplifier includes a bias source circuit and a bias generator circuit. The bias source circuit is for generating a reference current according to the first voltage and the second voltage. The bias generator circuit is for generating bias voltages according to the reference current. The startup circuit and the bandgap reference circuit receive a supply voltage.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a first gate structure on the substrate and adjacent to the STI, forming a first doped region between the first gate structure and the STI, forming a second doped region between the first doped region and the first gate structure, forming a first contact plug on the first doped region, and then forming a second contact plug on the second doped region.

Abstract: A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.

Abstract: A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.

Abstract: A command script editing method, a command script editor and a graphic user interface are provided. The command script editing method includes the following steps. The command node is edited according to at least one inputting action or at least one image identifying action performed on the operation frame when the command script editor is at an image editing mode. The command node is edited according to a setting content of at least one process action when the command script editor is at a process editing mode.

Abstract: A semiconductor device includes a logic circuit region having at least one core device and at least one input/output (I/O) device. The at least one core device has a first accumulative antenna ratio, and the at least one I/O device has a second accumulative antenna ratio. The first accumulative antenna ratio is greater than the second accumulative antenna ratio.

Abstract: The invention provides a semiconductor structure, which comprises a substrate, a gate dielectric layer on the substrate, wherein the gate dielectric layer comprises two sidewall portions and a horizontal portion between the two sidewall portions, wherein a height of the horizontal portion is lower than that of the two sidewall portions, and the horizontal portion and the two sidewall portions are perpendicular to each other, and a gate conductive layer on the horizontal portion of the gate dielectric layer.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a gate structure on the STI and the substrate, forming a patterned mask on the STI and the gate structure, performing an etching process to remove part of the STI for forming a first trench adjacent to one side of the gate structure and a second trench adjacent to another side of the gate structure, and then forming a contact etch stop layer (CESL) on the gate structure and into the first trench and the second trench.

Abstract: A random access memory, including a write transistor with a gate electrically connected to a write word line and a drain electrically connected to a write bit line, a first read transistor and a second read transistor with gates electrically connected to a source of the write transistor to form a storage node, drains electrically connected to a read bit line and a common source electrically connected to a read word line so that the first read transistor and a second read transistor are in parallel connection, and a capacitor electrically connected to the storage node.

Abstract: The invention provides a layout pattern of static random access memory, which comprises a plurality of fin structures on a substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate. The transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2), a first access transistor (PG1), a second access transistor (PG2), a first read port transistor (RPD) and a second read port transistor (RPG). The gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1), wherein a drain of the first pull-down transistor (PD1) is connected to a first voltage source Vss1, and a drain of the first read port transistor (RPD) is connected to a second voltage source Vss2.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a first mesa isolation on the HEMT region and a second mesa isolation on the capacitor region, forming a HEMT on the first mesa isolation, and then forming a capacitor on the second mesa isolation.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Abstract: A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.