Patents Assigned to Vanguard International Semiconductor Corporation
  • Publication number: 20240083743
    Abstract: A microelectromechanical systems (MEMS) package includes a first MEMS package and a second MEMS package laterally spaced apart from the first MEMS package. The first MEMS package includes a first device substrate including a first MEMS device, a first cap substrate bonded to the first device substrate, where the first cap substrate encloses a first cavity and a vent hole connected to the first cavity. A first sealing layer is filled in the vent hole, where the first sealing layer is disposed between the first device substrate and the first cap substrate. The second MEMS package includes a second device substrate including a second MEMS device and a second cap substrate. The second cap substrate is bonded to the second device substrate and encloses a second cavity. The first cavity has a first pressure, and the second cavity have a second pressure different from the first pressure.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: RAKESH CHAND, RAMACHANDRAMURTHY PRADEEP YELEHANKA, Sock Kuan Soo, Poh Liang Yap, GUOFU ZHOU
  • Patent number: 11929407
    Abstract: A method of fabricating a HEMT includes the following steps. A substrate having a group III-V channel layer, a group III-V barrier layer, a group III-V gate layer, and a gate etch stop layer disposed thereon is provided. A passivation layer is formed to cover the group III-V barrier layer and the gate etch stop layer. A gate contact hole and at least one source/drain contact hole are formed in the passivation layer, where the gate contact hole exposes the gate etch stop layer, and the at least one source/drain contact hole exposes the group III-V channel layer. In addition, a conductive layer is conformally disposed on a top surface of the passivation layer and in the gate contact hole and the at least one source/drain contact hole.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: March 12, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ting-En Hsieh, Yu-Chieh Chou, Yung-Fong Lin
  • Publication number: 20240061455
    Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang HUANG, Yeh-Ning JOU, Ching-Ho LI, Kai-Chieh HSU, Chun-Chih CHEN, Chien-Wei WANG, Gong-Kai LIN, Li-Fan CHEN
  • Publication number: 20240046997
    Abstract: A non-volatile memory device includes a set of memory cells, a cycle transistor, a reference transistor and a control circuit. The control circuit is coupled to the set of memory cells, the cycle transistor and the reference transistor. A method of controlling the non-volatile memory device includes in a program operation or an erase operation of the set of memory cells, the control circuit determining a state of the cycle transistor, and upon determining the cycle transistor being in an erased state (or a programmed state), the control circuit setting the reference transistor from a reference state to the erased state (or the programmed state), and then restoring the reference transistor from the erased state (or the programmed state) to the reference state. The reference state is set between the erased state and a programmed state.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 8, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventor: Po-Yuan Tang
  • Publication number: 20240047460
    Abstract: A semiconductor device includes a first buried layer and a second buried layer both have a first conductivity type and are disposed in a substrate, where the second buried layer is disposed on the first buried layer. A first well region has the first conductivity type and is disposed above the second buried layer. A second well region has a second conductivity type and is adjacent to the first well region. A deep trench isolation structure is disposed in the substrate and surrounds the first and second well regions, where the bottom surface of the deep trench isolation structure is lower than the bottom surface of the first buried layer. A source region is disposed in the second well region. A drain region is disposed in the first well region. A gate electrode is disposed on the first and second well regions.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 8, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Cherng Liao, Chung-Ren Lao, Hsing-Chao Liu, Chun-Wei Li, Hsueh-Chun Liao
  • Patent number: 11890643
    Abstract: A PMUT includes a substrate, a stopper, and a multi-layered structure, where the substrate includes a corner, and a cavity is disposed in the substrate. The stopper is in contact with the corner of the substrate and the cavity. The multi-layered structure is disposed over the cavity and attached to the stopper and the multi-layered structure includes at least one through hole in contact with the cavity.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: February 6, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: You Qian, Joan Josep Giner de Haro, Rakesh Kumar, Jia Jie Xia
  • Patent number: 11894674
    Abstract: A power detection circuit is provided. The protection circuit is coupled to a pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor of a first conductivity type and a second transistor, also of the first conductivity type, which are coupled in series between the pad and a ground terminal. The trigger circuit detects whether a transient even occurs on the pad. The discharge circuit is coupled between the bonding pad and the ground terminal and controlled by the trigger circuit. In response to the transient event occurring on the bonding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the pad and the ground terminal.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: February 6, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jian-Hsing Lee, Yeh-Ning Jou, Chih-Hsuan Lin, Chang-Min Lin, Hwa-Chyi Chiou
  • Patent number: 11894430
    Abstract: A semiconductor structure, including a substrate, a first well, a second well, a first doped region, a second doped region, a first gate structure, a first insulating layer, and a first field plate structure. The first and second wells are disposed in the substrate. The first doped region is disposed in the first well. The second doped region is disposed in the second well. The first gate structure is disposed between the first and second doped regions. The first insulating layer covers a portion of the first well and a portion of the first gate structure. The first field plate structure is disposed on the first insulating layer, and it partially overlaps the first gate structure. Wherein the first field plate structure is segmented into a first partial field plate and a second partial field plate separated from each other along a first direction.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: February 6, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Kai-Chieh Hsu, Chun-Chih Chen, Chih-Hsuan Lin
  • Publication number: 20240040932
    Abstract: A method of forming micro-electromechanical system (MEMS) device, the MEMS device includes a composite substrate, a cavity, a piezoelectric stacking structure and a proof mass. The composite substrate includes a first semiconductor layer, a bonding layer and a second semiconductor layer from bottom to top. The cavity is disposed in the composite substrate, and the cavity is extended from the second semiconductor layer into the first semiconductor layer and not penetrated the first semiconductor layer. The piezoelectric stacking structure is disposed on the composite substrate, with the piezoelectric stacking structure having a suspended region over the cavity. The proof mass is disposed in the cavity to connect to the piezoelectric stacking structure.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventor: Jia Jie Xia
  • Publication number: 20240028813
    Abstract: A semiconductor layout including a semiconductor layer and a dummy layer is provided. The semiconductor layer includes a layout pattern. The dummy layer includes a dummy pattern. A check circuit calculates the layout pattern and the dummy pattern to generate a calculated value. The check circuit compares the calculated value to the predetermined value to determine whether the layout pattern has been modified.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yeh-Ning JOU, Chih-Hsuan LIN, Shu-Pin HSU, Hwa-Chyi CHIOU, Chang-Min LIN, Tsong-Shyan CHEN
  • Patent number: 11878905
    Abstract: The present disclosure related to a micro-electromechanical system (MEMS) device and a method of forming the same. The MEMS device includes a substrate, a cavity, an interconnection structure and a proof mass. The substrate includes a first surface and a second surface opposite to the first surface. The cavity is disposed in the substrate to extend between the first surface and the second surface. The interconnection structure is disposed on the first surface of the substrate, over the cavity. The proof mass is disposed on the interconnection structure, wherein the proof mass is partially suspended over the interconnection structure.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: January 23, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Jia Jie Xia
  • Publication number: 20240021475
    Abstract: A semiconductor structure includes a substrate, several gate structures formed in the substrate, dielectric portions formed on the respective gate structures, spacers adjacent to and extending along the sidewalls of the dielectric portions, source regions formed between the substrate and the spacers, and contact plugs formed between adjacent gate structures and contact the respective source regions. The source regions are adjacent to the gate structures. The sidewalls of the spacers are aligned with the sidewalls of the underlying source regions.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 18, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Po-Hsiang LIAO, Sheng-Wei FU, Chung-Yeh LEE
  • Patent number: 11876118
    Abstract: A semiconductor structure includes a substrate, a gate structure on the substrate, and a source structure and a drain structure on opposite sides of the gate structure. The gate structure includes a gate electrode on the substrate and a gate metal layer on the gate electrode. The gate metal layer has at least one notch, which exposes the gate electrode below. The electric potential of the source structure is different from that of the gate structure.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: January 16, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shin-Cheng Lin, Cheng-Wei Chou
  • Publication number: 20230420328
    Abstract: A semiconductor device includes: a substrate; a seed layer disposed on the substrate; a compound semiconductor stack layer disposed on the seed layer; and a source metal layer and a drain metal layer disposed on the compound semiconductor stack layer. The semiconductor device further includes a conductive layer at least partially covering the source metal layer and the drain metal layer, and covering opposing side surfaces of the seed layer and opposing side surfaces of the compound semiconductor stack layer. The conductive layer electrically connects the seed layer and the source metal layer.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsiu-Mei YU, Guang-Yuan JIANG, Cheng-Yi HSIEH, Wei-Chan CHANG, Chang-Sheng LIN
  • Publication number: 20230420529
    Abstract: A semiconductor device includes a substrate, a body region on the substrate, a source region on the body region, a first trench electrode passing through the source region, the body region and a portion of the substrate, a first dielectric cap layer, a first dielectric liner and a conductive layer. The first dielectric cap layer includes a first dielectric portion directly above the first trench electrode and first dielectric spacers on two opposite sides of the first dielectric portion. The first dielectric liner surrounds the first trench electrode and the first dielectric portion. The conductive layer covers the first dielectric cap layer and includes an electrode contact. The electrode contact includes a first portion in the body region and a second portion adjacent to one of the first dielectric spacers, where the first and second portions have the same width.
    Type: Application
    Filed: June 26, 2022
    Publication date: December 28, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Po-Hsiang Liao, Sheng-Wei Fu, Chung-Yeh Lee
  • Publication number: 20230420560
    Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a semiconductor substrate, a well region, an isolation structure, a gate structure and a field doped region. The well region having a first conductivity type is disposed in the semiconductor substrate. The gate structure extends to cover a portion of the isolation structure in the well region. The field doped region having a second conductivity type is disposed on the well region. The field doped region has a first portion overlapping the isolation structure and a second portion that is connected to the first portion and away from the gate structure. A first depth between a bottom surface of the first portion and a top surface of the semiconductor structure is greater than a second depth between a bottom surface of the second portion and the top surface of the semiconductor structure.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 28, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventor: Yu-Hao HO
  • Publication number: 20230387103
    Abstract: A semiconductor structure is provided. At least one first well region is disposed in a semiconductor substrate and has a first conductivity type. At least one gate of a transistor is disposed over the first well region and extends in a first direction. At least one second well region and at least one third well region are disposed on opposite sides of the first well region and extend in the first direction. The second and third well regions have a second conductivity type. A first shielding structure is disposed on at least one end of the gate and partially overlaps the first well region in a vertical projection direction. The first shielding structure is separated from the end of the gate. A bulk ring is disposed in the semiconductor substrate and surrounds the gate, the second well region, the third well region, and the first shielding structure.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsien-Feng LIAO, Jian-Hsing LEE, Chieh-Yao CHUANG, Ting-Yu CHANG, Yeh-Ning JOU, Shao-Chang HUANG, Kan-Sen CHEN, Nai-Lun CHENG, Ching-Yi HSU, Yu-Chen WU
  • Publication number: 20230382713
    Abstract: A micro-electro-mechanical system (MEMS) device includes a first substrate, an interconnect layer, a MEMS device layer, a stopper and a second substrate. The interconnect layer is disposed on the first substrate and includes a plurality of conductive layers and a plurality of dielectric layer stacked alternately. The MEMS device layer is bonded on the interconnect layer and includes a proof mass. The stopper is disposed directly under the proof mass and spaced apart from the proof mass, where the stopper is surrounded by a portion of the interconnect layer, and the stopper includes a bottom portion constructed of one of the plurality of conductive layers, and a silicon-based layer disposed on the bottom portion. The second substrate includes a cavity and is bonded on the MEMS device layer.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: RAMACHANDRAMURTHY PRADEEP YELEHANKA, RAKESH CHAND, HUP FONG TAN, ROHIT PULIKKAL KIZHAKKEYIL, WAI MUN CHONG
  • Patent number: 11825750
    Abstract: A micro-electromechanical system (MEMS) device and a method of forming the same, the MEMS device includes a composite substrate, a cavity, a piezoelectric stacking structure and a proof mass. The composite substrate includes a first semiconductor layer, a bonding layer and a second semiconductor layer from bottom to top. The cavity is disposed in the composite substrate, and the cavity is extended from the second semiconductor layer into the first semiconductor layer and not penetrated the first semiconductor layer. The piezoelectric stacking structure is disposed on the composite substrate, with the piezoelectric stacking structure having a suspended region over the cavity. The proof mass is disposed in the cavity to connect to the piezoelectric stacking structure.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: November 21, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Jia Jie Xia
  • Publication number: 20230369848
    Abstract: A power detection circuit is provided. The protection circuit is coupled to a pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor of a first conductivity type and a second transistor, also of the first conductivity type, which are coupled in series between the pad and a ground terminal. The trigger circuit detects whether a transient even occurs on the pad. The discharge circuit is coupled between the bonding pad and the ground terminal and controlled by the trigger circuit. In response to the transient event occurring on the bonding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the pad and the ground terminal.
    Type: Application
    Filed: May 11, 2022
    Publication date: November 16, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Jian-Hsing LEE, Yeh-Ning JOU, Chih-Hsuan LIN, Chang-Min LIN, Hwa-Chyi CHIOU