Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes first, second, and third transistors and a discharge circuit. The first transistor has a first gate, a first drain coupled to the bonding pad, and a first source coupled to a first node. The second transistor has a second gate coupled to a power terminal, a second drain coupled to the first gate, and a second source coupled to a ground. The third transistor has a third gate coupled to the power terminal, a third drain coupled to the first node, and a third source coupled to the ground. The discharge circuit is controlled by a driving voltage at the first node. In response to an electrostatic discharge event occurring on the bonding pad, the discharge circuit provides a discharge path between the bonding pad and the ground according to the driving voltage.

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

Abstract: A semiconductor device includes a semiconductor layer, a deep trench isolation structure, a shallow trench isolation structure, a first resistance layer, a second resistance layer, a first heavily doped region, a second heavily doped region, and a conductive line. The deep trench isolation structure separates the semiconductor device into a plurality of units including the first and second units. The shallow trench isolation structure is disposed on a portion of the semiconductor layer in one of the plurality of units. The first and second resistance layers are disposed on the shallow trench isolation structure in the first and second units respectively. The first and second heavily doped regions are embedded in the shallow trench isolation structure and in physical contact with the semiconductor layer in the first and second units respectively. The conductive line electrically connects the first and second resistance layers and the second heavily doped region.

Abstract: A semiconductor structure includes a substrate, a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composite blocking layer. The buffer layer is on the substrate. The channel layer is on the buffer layer. The barrier layer is on the channel layer. The doped compound semiconductor layer is on the barrier layer. The composite blocking layer is on the doped compound semiconductor layer, the composite blocking layer and the barrier layer include the same Group III element, and the atomic percent of the same Group III element in the composite blocking layer increases with the distance from the doped compound semiconductor layer.

Abstract: A semiconductor structure including a substrate, a first well, a first doped region, a second doped region, a third doped region, a second well, a fourth doped region, and a fifth doped region is provided. The substrate has a first conductivity type. The first well is disposed in the substrate and has a second conductivity type. The first doped region is disposed in the first well and has the second conductivity type. The second doped region is disposed in the first well and has the first conductivity type. The third doped region is disposed in the first well and has the first conductivity type. The second well is disposed in the first well. The fourth doped region is disposed in the second well and has the first conductivity type. The fifth doped region is disposed in the second well and has the second conductivity type.

Abstract: An optical sensor device is provided. The optical sensor device includes a semiconductor substrate, an isolation feature, a first doped region, a second doped region, and a third doped region. The semiconductor substrate of a first conductivity type includes a sensing region surrounded by an isolation region. The first doped region of a second conductivity type is located in the sensing region. The second doped region of the second conductivity type is located in the sensing region and above the first doped region. The third doped region of the first conductivity type is located in the sensing region and on the second doped region. In a cross-sectional view, the first doped region has a first length, the second doped region has a second length, and a first ratio, which is the ratio of the second length to the first length, is greater than 0 and less than 1.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, an epitaxial layer, a well region, an insulating structure, an upper electrode layer, and a lower electrode layer. The substrate has the first conductivity type. The epitaxial layer is disposed on the substrate and has the first conductivity type. There is a protruding structure on the upper portion of the epitaxial layer. The well region is disposed in the epitaxial layer. The well region has the second conductivity type. The insulating structure is disposed on the sidewall of the protruding structure. The upper electrode layer surrounds the protruding structure and is electrically connected to the epitaxial layer and the well region. The lower electrode layer is disposed under the substrate and opposite to the epitaxial layer.

Abstract: A semiconductor device includes a gate electrode disposed on a substrate. A source region and a drain region are disposed in the substrate and located on two sides of the gate electrode respectively. The drain region includes a plurality of drain segments that are laterally separated from each other. These drain segments have a first conductive type and the substrate has a second conductive type. A plurality of drain contacts is electrically connected to the drain segments. Each drain segment corresponds to at least one of these drain contacts. A drain electrode is electrically connected to these drain contacts. A source electrode is electrically connected to the source region.

Abstract: A semiconductor structure including a substrate, an epitaxy layer, an electrode structure, a first sidewall doping region, a second sidewall doping region, and a bottom doping region is provided. The substrate has a first conductivity type. The epitaxy layer has a first conductivity type and is disposed on the substrate. The electrode structure is disposed in the epitaxy layer. The electrode structure extends along a first direction. The first sidewall doping region has the first conductivity type and is disposed on one side of the electrode structure. The second sidewall doping region has a second conductivity type different than the first conductivity type and is disposed on the other side of the electrode structure. The bottom doping region has the second conductivity type and is disposed under the electrode structure. The second sidewall doping region is connected to the bottom doping region.

Abstract: A semiconductor device includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate. A passivation layer covers the semiconductor barrier layer. A first gate electrode and a second gate electrode are laterally separated from each other and at least partially disposed in the passivation layer respectively. Along a first direction, a first gate length of the first gate electrode is less than a second gate length of the second gate electrode. A source electrode and a drain electrode are disposed on the semiconductor channel layer. The second gate electrode is electrically connected to the source electrode. The first gate electrode and the second gate electrode are electrically isolated from each other.

Abstract: A semiconductor device includes a substrate having an active element region and a passive element region. A compound semiconductor channel layer, a compound semiconductor barrier layer and a first compound semiconductor cap layer are disposed in sequence on the substrate and located in the active element region. A gate electrode is disposed on the first compound semiconductor cap layer. A source electrode and a drain electrode are disposed on the compound semiconductor barrier layer and located on two opposite sides of the gate electrode, respectively, to construct a high electron mobility transistor. A second compound semiconductor cap layer is disposed on the substrate and located in the passive element region to construct a resistor.

Abstract: A high electron mobility transistor structure includes a compound semiconductor channel layer disposed on a substrate, a compound semiconductor barrier layer disposed on the compound semiconductor channel layer, and a compound semiconductor cap layer disposed on the compound semiconductor barrier layer. The compound semiconductor cap layer includes a first segment and a second segment arranged along a first direction, and a gap between the first segment and the second segment. A gate electrode is disposed on the compound semiconductor cap layer. A source electrode and a drain electrode are disposed on the compound semiconductor barrier layer, arranged along a second direction and respectively located on two sides of the compound semiconductor cap layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a first deep well region, at least two second well regions, at least one isolation structure and an implantation region. The first deep well region is disposed in the semiconductor substrate, wherein the first deep well region has a first conductivity type. The second well regions are disposed on the first deep well region, wherein the second well regions have a second conductivity type. The isolation structure covers a portion of the first deep well region and surrounds at least a portion of the second well regions. The implantation region is located under a top surface of the semiconductor substrate, wherein the implantation region has a discontinuous portion, and the discontinuous portion partially overlaps the first deep well region.

Abstract: A micro-electro-mechanical system (MEMS) device includes a substrate having a cavity and a MEMS structure disposed over the cavity and attached to the substrate. The MEMS structure includes at least one first piezoelectric layer having a first piezoelectric coefficient and two second piezoelectric layers respectively disposed under and above the first piezoelectric layer, where each second piezoelectric layer has a second piezoelectric coefficient higher than the first piezoelectric coefficient. The MEMS structure further includes a first electrode layer and a second electrode layer sandwiching the two second piezoelectric layers.

Abstract: A high electron mobility transistor includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate field plate, a source electrode, at least one first field plate, and a second field plate. The gate field plate is disposed on the semiconductor barrier layer. The source electrode is disposed on one side of the gate field plate, and the first field plate is disposed on the other side of the gate field plate and laterally spaced apart from the gate field plate. The second field plate covers the gate field plate and the first field plate and is electrically connected to the source electrode, where the area of the second field plate is larger than the sum of the area of the gate field plate and the area of the first field plate when perceived from a top-down perspective.

Abstract: A driving circuit includes a detection circuit, a control circuit, and a power device. The detection circuit is coupled between first and second power terminals. The detection circuit generates a detection voltage at a detection node based on a first voltage of the first power terminal and a second voltage of the second power terminal. The control circuit includes a transistor device with a back-to-back connection structure that is coupled between a bonding pad and a first node and controlled by the detection voltage to generate a driving voltage at the first node for controlling the power device. In response to an electrostatic discharge event occurring on the bonding pad, the transistor device is turned on according to the detection voltage, and the power device is triggered by the driving voltage to provide a discharge path between the bonding pad and the second power terminal.

Abstract: A semiconductor device includes a substrate having a first conductivity type, an epitaxial layer on the substrate and having the first conductivity type, a trench structure extending from the top surface of the epitaxial layer into the epitaxial layer, and a well region extending into the epitaxial layer and has the second conductivity type. The first sidewall of the well region is in contact with the trench structure. The trench structure includes a conductive portion and an insulating layer that covers the sidewalls and the bottom portion of the conductive portion. A drift region that has the first conductivity type is adjacent to and under the well region. The drift region is in contact with the second sidewall and the bottom surface of the well region. The semiconductor device further includes a gate structure on the top surface of the epitaxial layer and over the well region.

Abstract: A semiconductor device includes a substrate, a first well region, a second well region, an isolation region, a first resistor segment and a second resistor segment. The substrate includes a region having a first conductivity type. The first and the second well regions are disposed in the region of the substrate. The isolation region is disposed on the first and the second well regions. The first and the second resistor segments are electrically connected to each other and disposed on the isolation region. Moreover, the first and the second well regions are disposed directly under the first and the second resistor segments, respectively. The first and the second well regions do not overlap with each other in a vertical projection direction and have a second conductivity type that is opposite to the first conductivity type.

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

Abstract: An ESD protection device includes a substrate, an epitaxial layer, first to third well regions, and first to sixth doped regions. The first to third well regions are disposed in the epitaxial layer. The third well region is disposed between the first and second well regions. The first and second doped regions are disposed on the first well region and coupled to a pad. The third and fourth doped regions are disposed on the second well region and coupled to a ground terminal. The fifth doped region is disposed on the third well region, and the sixth doped region is disposed in the fifth doped region. The third, fifth, and sixth doped regions have the same conductive type. In response to an electrostatic discharge event occurring on the pad, a discharge path is formed between the pad and the ground terminal.