Patents Assigned to Vanguard International Semiconductor Corporation
  • Patent number: 10446677
    Abstract: A semiconductor structure is provided. The semiconductor structure includes an insulating substrate including a first region and a second region; an engineered layer surrounding the insulating substrate; a nucleation layer formed on the engineered layer; a buffer layer formed on the nucleation layer; a first epitaxial layer formed on the buffer layer; a second epitaxial layer formed on the first epitaxial layer; an isolation structure at least formed in the second epitaxial layer, the first epitaxial layer and the nucleation layer, and located between the first region and the second region; a first gate, a first source and a first drain formed on the second epitaxial layer within the first region; and a second gate, a second source, and a second drain formed on the second epitaxial layer within the second region.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: October 15, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Francois Hebert
  • Publication number: 20190312154
    Abstract: A semiconductor device includes a substrate, a well region formed in the substrate, first and second isolation regions formed in the substrate, a dielectric layer formed on the well region, a conductive layer formed on the dielectric layer, a first doped region, an insulating layer, and first and second contact vias. The dielectric layer is disposed between the first and second isolation regions. The first doped region is formed in the well region. The insulating layer is formed on the dielectric layer, the first and second isolation regions, and the first doped region. The first contact via is formed in the insulating layer and electrically connected to the conductive layer. The first contact via is disposed on an overlapping area between the dielectric layer and the conductive layer. The second contact via is formed in the insulating layer and electrically connected to the doped region.
    Type: Application
    Filed: April 5, 2018
    Publication date: October 10, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Ching-Yi HSU, Shih-Hao LIU, Wu-Hsi LU, Yun-Chou WEI, Chih-Cherng LIAO
  • Publication number: 20190304837
    Abstract: A method for forming a semiconductor device is provided. The method includes providing a substrate, placing a first stencil having a first openwork pattern on the substrate, applying a first material onto the substrate through the first stencil, and removing the first stencil from the substrate. The first material includes a transparent material. The method also includes placing a second stencil having a second openwork pattern on the substrate, applying a second material onto the substrate through the second stencil, and removing the second stencil from the substrate. The second material includes a light-shielding material, and the second openwork pattern is different from the first openwork pattern.
    Type: Application
    Filed: September 20, 2018
    Publication date: October 3, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Han-Liang TSENG, Hsin-Hui LEE, Hsueh-Jung LIN
  • Publication number: 20190305128
    Abstract: A semiconductor structure includes an insulating layer, a semiconductor layer, and an epitaxial layer. The insulating layer is disposed on a substrate. The semiconductor layer is disposed on the insulating layer. The semiconductor layer includes a first buried layer and a second buried layer. The first buried layer has a first conductivity type. The second buried layer is disposed over the first buried layer and has a second conductivity type opposite to the first conductivity type. The second buried layer has at least two portions separate from each other. The epitaxial layer is disposed on the semiconductor layer.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 3, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Ankit KUMAR, Chia-Hao LEE, Jui-Chun CHANG
  • Patent number: 10431465
    Abstract: A method of fabricating a semiconductor structure includes providing a semiconductor substrate, forming a trench in the semiconductor substrate, overfilling the trench with a first semiconductor material, wherein the first semiconductor material does not have a dopant, forming a second semiconductor material on the first semiconductor material, wherein the second semiconductor material contains a dopant, and performing a thermal treatment so that the dopant in the second semiconductor material diffuses into the first semiconductor material to form a doped third semiconductor material in the trench.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: October 1, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Ming Kao, Rong-Gen Wu, Han-Wen Chang, Chun-Hsu Chen, Yu-Chun Ho
  • Patent number: 10431676
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a first III-V group compound semiconductor layer disposed on the substrate. The first III-V group compound semiconductor layer includes a fin structure having a top surface, a first sidewall, and a second sidewall opposite to the first sidewall. The semiconductor device also includes a second III-V group compound semiconductor layer disposed on the first III-V group compound semiconductor layer. The first III-V group compound semiconductor layer and the second III-V group compound semiconductor layer are made of different materials. The semiconductor device also includes a gate electrode disposed on the second III-V group compound semiconductor layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 1, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Chih Lin, Yu-Chieh Chou
  • Patent number: 10424659
    Abstract: A high electron mobility transistor includes a buffer layer, a threshold voltage adjustment layer, a band adjustment layer, a first enhancement layer, a gate electrode, and source/drain electrodes. The threshold voltage adjustment layer is disposed on the buffer layer. A channel region is disposed in the buffer layer adjacent to an interface between the buffer layer and the threshold voltage adjustment layer. The band adjustment layer is disposed on the threshold voltage adjustment layer. The first enhancement layer is conformally covering the threshold voltage adjustment layer and the band adjustment layer. The gate electrode is disposed on the first enhancement layer. The source/drain electrodes are disposed on the buffer layer through the threshold voltage adjustment layer and the first enhancement layer on opposite sides of the gate electrode respectively. The threshold voltage adjustment layer and the first enhancement layer are III-V semiconductors.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: September 24, 2019
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Hsin-Chih Lin, Yung-Hao Lin, Chia-Ching Huang
  • Publication number: 20190288099
    Abstract: A semiconductor structure is provided. The semiconductor structure includes an insulating substrate including a first region and a second region; an engineered layer surrounding the insulating substrate; a nucleation layer formed on the engineered layer; a buffer layer formed on the nucleation layer; a first epitaxial layer formed on the buffer layer; a second epitaxial layer formed on the first epitaxial layer; an isolation structure at least formed in the second epitaxial layer, the first epitaxial layer and the nucleation layer, and located between the first region and the second region; a first gate, a first source and a first drain formed on the second epitaxial layer within the first region; and a second gate, a second source, and a second drain formed on the second epitaxial layer within the second region.
    Type: Application
    Filed: March 16, 2018
    Publication date: September 19, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventor: Francois HEBERT
  • Patent number: 10418282
    Abstract: A method for forming an isolation structure of a semiconductor device is provided. The method includes forming a patterned dielectric structure in a first area and a second area of a substrate; forming a first isolation structure in the first area and forming a second isolation structure in the second area of the substrate; forming a cap layer over the first area and the second area of the substrate and performing an etching process to etch the cap layer of the second area completely; and performing an oxidation process on the second area to form a first oxide region over the second isolation structure and under the bottom surface of the patterned dielectric structure of the second area.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: September 17, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Pi-Kuang Chuang, Ching-Yi Hsu, Po-Sheng Hu
  • Publication number: 20190280092
    Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other. A method for fabricating the semiconductor device is also provided.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 12, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih LIN, Chang-Xiang HUNG, Chia-Ching HUANG, Yung-Hao LIN, Chia-Hao LEE
  • Publication number: 20190267455
    Abstract: An LDMOS includes a body region disposed in the substrate and having a first conductivity type; a drift region disposed in the substrate and having a second conductivity type; a source region disposed in the body region and having the second conductivity type; a drain region disposed in the drift region and having the second conductivity type; an isolation region disposed in the drift region between the source region and the drain region; a gate disposed on the body region and the drift region; a source field plate electrically connected to the source region; a drain field plate electrically connected to the drain region; and a first gate plate electrically connected to the gate. The first gate plate is correspondingly disposed above the gate. The shapes of the first gate plate and the gate are substantially the same when viewed from a top view.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 29, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin LIN, Yu-Hao HO, Shin-Cheng LIN, Cheng-Tsung WU
  • Patent number: 10396196
    Abstract: A semiconductor device includes a substrate, a semiconductor layer, a doped region, a device region, a first isolation structure, a second isolation structure and a terminal. The semiconductor layer is disposed over the substrate. The doped region is disposed in the semiconductor layer. The device region is disposed on the doped region and includes a source, a drain and a gate. The first isolation structure is disposed in the semiconductor layer and surrounds the doped region. The second isolation structure surrounds the first isolation structure and is spaced apart from the first isolation structure. The terminal is disposed between the first isolation structure and the second isolation structure, and is equipotential with the source.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: August 27, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jui-Chun Chang, Shih-Kai Wu, Cheng-Yu Wang, Li-Yang Hong, Chia-Ming Hsu
  • Patent number: 10395085
    Abstract: Embodiments of the disclosure relate to a semiconductor device. The semiconductor device includes a semiconductor substrate, a first metal wiring layer disposed on the semiconductor substrate, an interlayer dielectric layer (ILD) disposed on the first metal wiring layer, a second metal wiring layer disposed on the interlayer dielectric layer, and a first via and a second via disposed in the interlayer dielectric layer. The second via is on the first via, and there is not any metal wiring layer in the interlayer dielectric layer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 27, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shih-Hao Liu, Leuh Fang, Chih-Cherng Liao, Yun-Chou Wei, Chung-Ren Lao, Wu-Hsi Lu
  • Patent number: 10388649
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate includes a first region and a second region. The semiconductor device also includes a buried layer disposed in the first region of the semiconductor substrate and having the first conductivity type, wherein the buried layer has a dopant concentration that is greater than that of the semiconductor substrate. The semiconductor device further includes an epitaxial layer disposed on the semiconductor substrate, and a first element disposed on the first region of the semiconductor substrate, wherein the first element includes a bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) (BCD) transistor. In addition, the semiconductor device includes a second element disposed on the second region of the semiconductor substrate, wherein the second element includes an ultra-high voltage (UHV) transistor.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: August 20, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chien-Wei Chiu, Shin-Cheng Lin, Yu-Hao Ho
  • Patent number: 10388758
    Abstract: A method for fabricating a semiconductor structure includes providing a substrate. The method further includes implanting the substrate to form a high-voltage well region having a first conductivity type. The method further includes forming a pair of drain drift regions in the high-voltage well region. The pair of drain drift regions are on the front side of the substrate, and the pair of drain drift regions have a second conductivity type opposite to the first conductivity type. The method further includes forming a gate electrode embedded in the high-voltage well region. The gate electrode is positioned between the pair of drain drift regions and laterally spaced apart from the pair of drain drift regions.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: August 20, 2019
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Cherng Liao, Manoj Kumar, Chia-Hao Lee, Chung-Te Chou, Ya-Han Liang
  • Publication number: 20190252505
    Abstract: A HEMT device is provided. The HEMT device includes a substrate, a buffer layer, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, a drain, a trench, and a metal layer. The buffer layer is formed on the substrate. The first epitaxial layer is formed on the buffer layer. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is disposed in the insulating layer. The source and the drain are disposed in the insulating layer. The trench passes through the insulating layer and the second epitaxial layer, and extends into the first epitaxial layer. The metal layer is formed on the insulating layer to connect to the source, and is filled into the trench to electrically connect to the first epitaxial layer and the source.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih LIN, Shin-Cheng LIN, Yung-Hao LIN
  • Patent number: 10381303
    Abstract: Semiconductor device structures are provided. The semiconductor device structures include a semiconductor substrate. The semiconductor device structures also include an inner metal layer disposed on the semiconductor substrate and a top metal layer disposed on the inner metal layer, wherein the top metal layer has a first portion and a second portion, and wherein the first portion completely covers the inner metal layer, the second portion surrounds the first portion, and the first portion is separated from the second portion. The semiconductor device structures further include a passivation layer disposed on the top metal layer, wherein the passivation layer has a hollowed pattern to expose the top metal layer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 13, 2019
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ting-You Lin, Chi-Li Tu
  • Publication number: 20190229206
    Abstract: A method for fabricating a semiconductor structure includes providing a substrate. The method further includes implanting the substrate to form a high-voltage well region having a first conductivity type. The method further includes forming a pair of drain drift regions in the high-voltage well region. The pair of drain drift regions are on the front side of the substrate, and the pair of drain drift regions have a second conductivity type opposite to the first conductivity type. The method further includes forming a gate electrode embedded in the high-voltage well region. The gate electrode is positioned between the pair of drain drift regions and laterally spaced apart from the pair of drain drift regions.
    Type: Application
    Filed: January 22, 2018
    Publication date: July 25, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Cherng LIAO, Manoj KUMAR, Chia-Hao LEE, Chung-Te CHOU, Ya-Han LIANG
  • Publication number: 20190229209
    Abstract: A semiconductor device includes a first gallium nitride layer disposed on a semiconductor substrate, and an aluminum gallium nitride layer disposed on the first gallium nitride layer. The semiconductor device also includes an upper recess and a lower recess disposed in the aluminum gallium nitride layer, wherein the upper recess adjoins the lower recess, and the upper recess has a width that is greater than that of the lower recess. The semiconductor device further includes a second gallium nitride layer disposed in the first recess and the second recess, and a gate structure disposed on the second gallium nitride layer. In addition, the semiconductor device includes a source electrode and a drain electrode disposed on the aluminum gallium nitride layer.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 25, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chia-Hao LEE, Manoj KUMAR, Chang-Xiang HUNG, Chih-Cherng LIAO
  • Patent number: 10355096
    Abstract: A HEMT device is provided. The HEMT device includes a substrate, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, and a drain. The first epitaxial layer is formed on the substrate. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is formed in the insulating layer and extends into the second epitaxial layer. The source and the drain are formed in the insulating layer and extend into the second epitaxial layer, wherein the source and the drain are located on both sides of the gate.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: July 16, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Chih Lin, Shin-Cheng Lin, Yung-Hao Lin