Abstract: A Lamb wave resonator includes a piezoelectric material layer, a first finger electrode, a second finger electrode, at least two floating electrodes, and at least two gaps. The first finger electrode is disposed on one side of the piezoelectric material layer and includes a first main portion and first fingers. The second finger electrode is disposed on the side of the piezoelectric material layer and includes a second main portion and second fingers. The first fingers are parallel to and alternately arranged with the second fingers. The floating electrodes are disposed between each first finger and each second finger, and the gaps are disposed at two ends of each floating electrode, respectively.

Abstract: A structure of transferring dies includes an oxide layer supporting feature, multiple dies, a bonding feature, a supporting wafer, and a spacer. The oxide layer supporting feature includes multiple repeating units. Each repeating unit has a die setting region and a peripheral region. The die setting region of one repeating unit is separated from the peripheral region of another adjacent repeating unit. The die is disposed on the die setting region and the bonding feature is disposed on the peripheral region of the oxide layer supporting feature. The supporting wafer is disposed under the oxide layer supporting feature and separated from the die and the bonding feature by a gap. The spacer is disposed between the bonding feature and the supporting wafer, and bonded to the bonding feature.

Abstract: A micro-electro-mechanical system (MEMS) device includes a supporting substrate, a cavity disposed in the supporting substrate, a stopper, and a MEMS structure. The stopper is disposed between the supporting substrate and the cavity, and an inner sidewall of the stopper is in contact with the cavity. The stopper includes a filling material surrounding a periphery of the cavity, and a liner wrapping around the filling material. The MEMS structure is disposed over the cavity and attached on the stopper and the supporting substrate.

Abstract: A semiconductor structure includes a nucleation layer disposed on a substrate, an epitaxial growth layer disposed above the nucleation layer, and a superlattice structure disposed between the nucleation layer and the epitaxial growth layer. The superlattice structure includes a plurality of alternately stacked superlattice units, and adjacent two superlattice units include a first superlattice unit and a second superlattice unit. The first superlattice unit includes a first superlattice layer and a second superlattice layer stacked thereon, the second superlattice unit includes a third superlattice layer and a fourth superlattice layer stacked thereon, where each of the first, second, third and fourth superlattice layers includes a plurality of pairs of two sublayers with different compositions from each other.

Abstract: A PMUT includes a substrate, a membrane, and a sacrificial layer. The substrate has a cavity penetrating the substrate. The membrane is disposed over the cavity and includes a first piezoelectric layer, a bottom electrode, a top electrode, and a second piezoelectric layer. The first piezoelectric layer is disposed over the cavity and includes an anchor portion, where the anchor portion of the first piezoelectric layer is in direct contact with the substrate. The top and bottom electrodes are disposed over the first piezoelectric layer. The second piezoelectric layer is disposed between the bottom electrode and the top electrode. The sacrificial layer is disposed between the substrate and the first piezoelectric layer, and a vertical projection of the sacrificial layer does not overlap a vertical projection of portions of the membrane disposed over the cavity.

Abstract: A diode structure includes a substrate having a first conductivity type, a first well region having a second conductivity type opposite to the first conductivity type and disposed in the substrate, a first doped region having the first conductivity type and disposed in the first well region, a ring-shaped well region having the second conductivity type, disposed in the first well region and surrounding the first doped region, an anode disposed on the first doped region, a second well region having the second conductivity type, separated from the first well region and disposed in the substrate, a second doped region having the second conductivity type and disposed in the second well region, and a cathode disposed on the second doped region.

Abstract: A semiconductor device includes an insulating layer, a semiconductor layer, and a compound semiconductor stacked layer disposed on a substrate in sequence, a first transistor, a second transistor, an isolation structure, and a conductive structure. The first transistor is disposed in a first device region and on the compound semiconductor stacked layer. The second transistor is disposed in a second device region and on the compound semiconductor stacked layer. The isolation structure is disposed between the first and second transistors. The conductive structure is disposed in the second device region, passes through the compound semiconductor stacked layer, and electrically connects the semiconductor layer to a second source of the second transistor. There is no electrical connection between the semiconductor layer in the first device region and a first source of the first transistor.

Abstract: A storage device including a cell array and a disturb-free circuit is provided. The cell array includes a first cell and a second cell. The first cell is coupled to a first conductive line and a specific conductive line. The second cell is coupled to a second conductive line and the specific conductive line. The disturb-free circuit performs a first write operation on the first cell and performs a verification operation on the second cell. The verification operation determines whether data stored in the second cell is disturbed by the first write operation. In response to the data stored in the second cell being disturbed by the first write operation, the disturb-free circuit performs a second write operation.

Abstract: A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.

Abstract: An electronic device including a first transistor, a second transistor, a third transistor, and a resistance element is provided. The first transistor includes a first gate and is coupled between a first electrode and a second electrode. The second transistor includes a second gate, a third electrode, and a fourth electrode. The second gate is coupled to the second electrode. The third electrode is coupled to a control electrode. The third transistor includes a third gate, a fifth electrode, and a sixth electrode. The third gate is coupled to the control electrode. The fifth electrode is coupled to the fourth electrode. The sixth electrode is coupled to the second electrode. The resistance element is coupled between the third electrode and the first gate.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a lead frame and a sub-substrate disposed on the lead frame, wherein the thickness of the sub-substrate is between 0 and 0.5 ?m. The semiconductor structure also includes an epitaxial layer disposed on the sub-substrate. The epitaxial layer includes a buffer layer, a channel layer and a barrier layer. The buffer layer is disposed between the sub-substrate and the channel layer. The channel layer is disposed between the buffer layer and the barrier layer. The semiconductor structure further includes a device layer disposed on the barrier layer and an interconnector structure electrically connected to the epitaxial layer and/or the device layer by a through hole.

Abstract: A semiconductor device includes a substrate, a first well region, a second well region, an isolation region, a first resistor segment and a second resistor segment. The substrate includes a region having a first conductivity type. The first and the second well regions are disposed in the region of the substrate. The isolation region is disposed on the first and the second well regions. The first and the second resistor segments are electrically connected to each other and disposed on the isolation region. Moreover, the first and the second well regions are disposed directly under the first and the second resistor segments, respectively. The first and the second well regions do not overlap with each other in a vertical projection direction and have a second conductivity type that is opposite to the first conductivity type.

Abstract: A semiconductor device, including: a substrate having a first conductive type, an epitaxial layer disposed on the substrate, a doped region disposed in the epitaxial layer, and a gate electrode disposed through the doped region and extending into the epitaxial layer. The epitaxial layer has the first conductive type, and the doped region has a second conductive type different from the first conductive type. The gate electrode includes a first structure having a first dimension, and a second structure above the first structure. The second structure includes a main portion and a protruding portion below the main portion, wherein the main portion has a second dimension larger than the first dimension, and the protruding portion has the first dimension.

Abstract: An electrostatic discharge (ESD) protection circuit including a detection circuit, a voltage-divider element, and a discharge element is provided. The detection circuit is coupled between a first power line and a second power line. In response to an ESD event, the detection circuit enables a turn-on signal. The voltage-divider element is coupled between the first power line and a third power line and receives the turn-on signal. The discharge element is coupled between the second and third power lines. In response to the turn-on signal being enabled, the first discharge element discharges an ESD current.

Abstract: A storage device including a cell array and a disturb-free circuit is provided. The cell array includes a first cell and a second cell. The first cell is coupled to a first conductive line and a specific conductive line. The second cell is coupled to a second conductive line and the specific conductive line. The disturb-free circuit performs a first write operation on the first cell and performs a verification operation on the second cell. The verification operation determines whether data stored in the second cell is disturbed by the first write operation. In response to the data stored in the second cell being disturbed by the first write operation, the disturb-free circuit performs a second write operation.

Abstract: A method of fabricating a semiconductor structure includes forming a GaN-based semiconductor layer on a substrate, forming a silicon-containing insulating layer on the GaN-based semiconductor layer, forming a recess in the silicon-containing insulating layer in a first etching step, wherein the first etching step is performed by using a fluorine-containing etchant and applying a first bias power, and enlarging the recess to extend into the GaN-based semiconductor layer in a second etching step, wherein the second etching step is performed by using the same fluorine-containing etchant as the first etching step and applying a second bias power that is greater than the first bias power. In addition, a method of fabricating a high electron mobility transistor is provided.

Abstract: A semiconductor structure includes a substrate, a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composite blocking layer. The buffer layer is on the substrate. The channel layer is on the buffer layer. The barrier layer is on the channel layer. The doped compound semiconductor layer is on the barrier layer. The composite blocking layer is on the doped compound semiconductor layer, the composite blocking layer and the barrier layer include the same Group III element, and the atomic percent of the same Group III element in the composite blocking layer increases with the distance from the doped compound semiconductor layer.

Abstract: A semiconductor structure includes a substrate, a channel layer, a barrier layer, a source structure, a drain structure, a doped compound semiconductor layer, a dielectric layer, and a gate structure. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source structure and the drain structure are disposed on opposite sides of the barrier layer. The doped compound semiconductor layer is disposed on the barrier layer. The doped compound semiconductor layer has a first side adjacent to the source structure and a second side adjacent to the drain structure. The doped compound semiconductor layer has at least one opening exposing at least a portion of the barrier layer. The dielectric layer is disposed on the doped compound semiconductor layer and the barrier layer. The gate structure is disposed on the doped compound semiconductor layer.

Abstract: A semiconductor device is provided, including a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, an electrode structure on the epitaxial layer and an electric field modulation structure. The electrode structure includes a gate structure, a source structure and a drain structure, wherein the source structure and the drain structure are positioned on opposite sides of the gate structure. The electric field modulation structure includes an electric connection structure and a conductive layer electrically connected to the electric connection structure. The conductive layer is positioned between the gate structure and the drain structure. The electric connection structure is electrically connected to the source structure and the drain structure.

Abstract: A semiconductor substrate is provided. The semiconductor substrate includes a ceramic base, a seed layer, and a nucleation layer. The ceramic base has a front surface and a back surface, and the front surface is a non-flat surface. The seed layer is disposed on the front surface of the ceramic substrate. The nucleation layer is disposed on the seed layer.