Abstract: A capacitive biosensor is provided. The capacitive biosensor includes: a transistor, an interconnect structure on the transistor, and a passivation layer on the interconnect structure. The interconnect structure includes a first metal structure on the transistor, a second metal structure on the first metal structure, and a third metal structure on the second metal structure. The third metal structure includes a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked. The passivation has an opening exposing a portion of the third metal structure. The capacitive biosensor further includes a sensing region on the interconnect structure. The sensing region includes a first sensing electrode and a second sensing electrode. The first sensing electrode is formed of the third conductive layer, and the second sensing electrode is disposed on the passivation layer.

Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to form a groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.

Abstract: A magnetoresistive device includes a magnetoresistor disposed over a substrate, a stress release structure covering a side surface of the magnetoresistor, an electrical connection structure disposed over the magnetoresistor, and a passivation layer disposed over the electrical connection structure and the stress release structure.

Abstract: A semiconductor device including a substrate, a seed layer, a buffer layer, a channel layer, a barrier layer, a gate structure, a first source/drain structure, a second source/drain structure, and a contact is provided. The seed layer is disposed on the substrate. The buffer layer is disposed on the seed layer. The channel layer is disposed on the buffer layer. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The first and second source/drain structures are disposed on opposite sides of the gate structure. The contact contacts the first source/drain structure. The distance between the gate structure and the contact is between 0.5 micrometers and 30 micrometers.

Abstract: A semiconductor device includes at least one transistor, a shallow well region, a guard ring, and a plurality of first and second doped regions. The transistor is on a substrate and includes a source structure, a gate structure, and a drain structure. The shallow well region surrounds the transistor. The shallow well region has a first conductivity type. The guard ring surrounds the shallow well region. The guard ring has the first conductivity type. The first and second doped regions are disposed on the guard ring and surround the well region. The first doped regions and the second doped regions are alternately arranged in a shape of a loop. Each of the first doped regions and each of the second doped regions have opposite conductivity types.

Abstract: A high-voltage semiconductor device includes a substrate, a body region, a well region, a bulk region, a source, a drain, an isolation region, a gate structure, and a resistor. The body region and the well region are disposed in the substrate. The bulk region and the source are disposed in the body region. The drain is disposed in the well region. The isolation region is disposed on the well region. The isolation region is disposed between the drain and the source. The gate structure is disposed on the substrate. The gate structure extends onto a portion of the isolation region. The resistor is disposed on the isolation region. The resistor is electrically connected to the bulk region and the drain, or the resistor is electrically connected to the drain and/or the source.

Abstract: An electrical contact structure and a method for forming the electrical contact structure are provided. The method includes forming a thin film material layer on a substrate, forming a first barrier layer on the thin film material layer and forming a metal layer on the first barrier layer. The method further includes patterning the metal layer to form a metal pattern, forming a spacer on a sidewall of the metal pattern and covering a portion of the first barrier layer. The method further includes etching the first barrier layer, wherein the portion of the first barrier layer located under the spacer is not completely etched. The method further includes removing the spacer and exposing the sidewall of the metal pattern to form an electrical contact structure on the thin film material layer, wherein the first barrier layer has a protrusion part exceeding the sidewall of the metal pattern.

Abstract: A semiconductor device includes a substrate, an epitaxial layer, an emitter region, and a collector region. The epitaxial layer is disposed over the substrate and has a first conductivity type. The drift region is disposed in the epitaxial layer and has a second conductivity type that is the opposite of the first conductivity type. The emitter region is disposed in the epitaxial layer outside the drift region. The collector region is disposed in the drift region. The semiconductor device also includes a doped region. The doped region is disposed adjacent to the bottom surface of the drift region and has the first conductivity type.

Abstract: A semiconductor device is provided. The semiconductor device includes a channel layer disposed on a substrate, a barrier layer disposed on the channel layer, and a nitride layer disposed on the barrier layer. The semiconductor device also includes a compound semiconductor layer that includes an upper portion and a lower portion, wherein the lower portion penetrates through the nitride layer and a portion of the barrier layer. The semiconductor device also includes a spacer layer conformally disposed on a portion of the barrier layer and extending onto the nitride layer. The semiconductor device further includes a gate electrode disposed on the compound semiconductor layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extends through the spacer layer, the nitride layer, and at least a portion of the barrier layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a light-collimating layer. The substrate has a plurality of pixels. The light-collimating layer is disposed on the substrate, and the light-collimating layer includes a transparent material layer, a first light-shielding layer, a second light-shielding layer and a plurality of transparent pillars. The transparent material layer covers the pixels. The first light-shielding layer is disposed on the substrate and the first light-shielding layer has a plurality of holes corresponding to the pixels. The second light-shielding layer is disposed on the first light-shielding layer. The transparent pillars are disposed in the second light-shielding layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: An optical sensor includes pixels disposed in a substrate. A light collimating layer is disposed on the substrate and includes a transparent layer, a light-shielding layer, and transparent pillars. The transparent layer blanketly disposed on the substrate covers the pixels and the region between the pixels. The light-shielding layer is disposed on the transparent layer and between the transparent pillars. The transparent pillars penetrating through the light-shielding layer are correspondingly disposed on the pixels.

Abstract: A high electron mobility transistor includes a channel layer, a barrier layer, a first compound semiconductor layer, and a second compound semiconductor layer. The channel layer is disposed on the substrate, and the barrier layer is disposed on the channel layer. The first compound semiconductor layer is disposed on the barrier layer. The second compound semiconductor layer is disposed between the barrier layer and the first compound semiconductor layer, where the first compound semiconductor layer and the second compound semiconductor layer include a concentration distribution of metal dopant, and the concentration distribution of metal dopant includes a first peak in the first compound semiconductor layer and a second peak in the second compound semiconductor layer.

Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to forma groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.

Abstract: A test circuit testing a storage circuit and including a controller, a pattern-generator circuit, a comparing circuit, and a first register is provided. The storage circuit includes a storage block. The controller is configured to generate a plurality of internal test signals. The pattern-generator circuit generates and provides test data to the storage circuit according to the internal test signal. The storage circuit writes the test data into the storage block and reads the storage block to generate read data. The comparing circuit compares the test data and the read data to generate a test result. The first register stores the test result. The controller determines whether the storage circuit is working normally according to the test result stored in the first register.

Abstract: An electrostatic discharge protection (ESD) circuit is provided for a semiconductor element. The semiconductor element includes first and second drain/source electrodes and is surrounded by a deep well region. The ESD circuit includes a first control circuit and a first discharge circuit. The first control circuit is electrically connected between the first drain/source electrode and a power terminal and includes a first control terminal electrically connected to the deep well region and generates a first control signal. The first discharge circuit is controlled by the first control signal. When an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit generates the first control signal according to potential states of the deep well region and the first drain/source electrode, and the first discharge circuit provides a first discharge path between the first drain/source electrode and the power terminal according to the first control signal.

Abstract: A semiconductor device is provided, including a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, an electrode structure on the epitaxial layer and an electric field modulation structure. The electrode structure includes a gate structure, a source structure and a drain structure, wherein the source structure and the drain structure are positioned on opposite sides of the gate structure. The electric field modulation structure includes an electric connection structure and a conductive layer electrically connected to the electric connection structure. The conductive layer is positioned between the gate structure and the drain structure. The electric connection structure is electrically connected to the source structure and the drain structure.

Abstract: A package structure is provided. The package structure includes a die, a lead frame, and a conductive glue. The lead frame includes a die pad and a retaining wall structure. The die pad is configured to support the die, and the retaining wall structure surrounds the die. The conductive glue is disposed between the die and the lead frame.

Abstract: An access method for a memory device is provided. The access method includes receiving external data; reading a plurality of first memory cells of the memory device according to a write address to obtain first original data; comparing the external data and the first original data to determine whether the number of specific cells among the first memory cells is higher than a predetermined value, wherein the value of each of the specific cells would be changed from a first value to a second value in response to the external data being written into the first memory cells; and reversing the external data to generate reversed data and writing the reversed data into the first memory cells to replace the first original data in response to the number of specific cells being higher than the predetermined value.

Abstract: A semiconductor structure includes a substrate, a channel layer, a barrier layer, a source structure, a drain structure, a doped compound semiconductor layer, a dielectric layer, and a gate structure. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source structure and the drain structure are disposed on opposite sides of the barrier layer. The doped compound semiconductor layer is disposed on the barrier layer. The doped compound semiconductor layer has a first side adjacent to the source structure and a second side adjacent to the drain structure. The doped compound semiconductor layer has at least one opening exposing at least a portion of the barrier layer. The dielectric layer is disposed on the doped compound semiconductor layer and the barrier layer. The gate structure is disposed on the doped compound semiconductor layer.