Abstract: A nonvolatile memory device utilizing a program junction region of a p-type impurity and oxide grown thereon. In one aspect, the device comprises a programming structure and a program junction separated from said programming structure by a field oxide region. A program junction oxide layer overlies said program junction region. A floating gate is provided over the oxide which covers said programming structure, said program junction oxide layer, and in some embodiments the gate oxide of a sense transistor.

Abstract: A voltage switch is provided made up of 2.5 volt process transistors which tolerate a maximum gate to source, gate to drain, or drain to source voltage of 2.7 volts. The voltage switch transistors are arranged to switch between a voltage, such as 2.5 volts, and a much higher voltage, such as 4.5 volts. In one embodiment (350), the voltage switch includes an input provided to the source of an NMOS cascode connected transistor (360). An inverter (354) connects the source of the NMOS cascode (360) to the source of another NMOS cascode (361). A cascode transistor is defined as being connected so that it is turned on and off by varying source voltage with the gate voltage fixed, rather than varying gate voltage. Gates of the cascodes (360, 361) are connected to Vcc (2.5 volts). PMOS cascode transistors (362) and (363) connect the drains of respective cascode transistors (360) and (361) to PMOS transistors (364) and (365). The PMOS transistors (364) and (365) have sources connected to 4.5 volts.

Abstract: A high voltage detector circuit (FIG. 2) maintains a voltage (V.sub.2) on a reference line driven by a charge pump by turning the charge pump on with a signal (PUMPON) when the reference line voltage (V.sub.2) drops below a reference voltage (V.sub.1) plus a CMOS transistor threshold voltage. The high voltage detector is further configured to use transistors which have a maximum gate to drain, or gate to source voltage which exceeds the pin supply voltage to the chip. The high voltage detector includes comparators made up of a series of current mirrors driven by weak current sources enabling the circuit to use a minimum amount of power.

Abstract: A logic array device has an array of plural interconnect resources including plural lines and plural switchbox areas, with an array of plural Variable Grain Blocks (VGB's) interspersed within the array of plural interconnect resources. The array of plural interconnect resources does not regularly include lines of single-length or shorter, and the array of plural interconnect resources does not regularly include switchbox areas that are spaced apart from one another by distances of a single-length or shorter. The single-length corresponds to a traverse of a continuous distance covering approximately one VGB.

Abstract: A non-volatile memory cell structure which includes a floating gate, at least one injection element and a sense transistor. The injection element is at least partially formed in a first polysilicon layer. The floating gate is provided in a second polysilicon layer and capacitively coupled to the reverse breakdown element. The sense transistor is at least partially formed in a region of a semiconductor substrate, and connected to the floating gate. The structure may further comprise a control gate capacitively coupled to the floating gate and may be formed in said first polysilicon layer.

Abstract: A tileable structure is provided for logic array devices. The tileable structure has a mirror-symmetrical arrangement of sets of logic blocks, common control sections for the logic block sets, surrounding interconnect lines, and switching areas at intersections of the interconnect lines.

Abstract: A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions.

Abstract: The present invention is a method for fabricating a plurality of oxide regions having a plurality of thicknesses on a semiconductor wafer. The present invention includes a step of depositing a first masking layer on the semiconductor wafer, and the first masking layer defines at least one first region for oxide growth of a first thickness. The present invention also includes a step of implanting oxygen ions into the at least one first region such that the first thickness of oxide on the at least one first region is relatively thicker. The first masking layer is then removed from the semiconductor wafer. The present invention further includes a step of depositing a second masking layer on the semiconductor wafer, and the second masking layer defines at least one second region for oxide growth of a second thickness.

Abstract: A phase locked loop comprises a phase locking circuit (16) which includes a phase/frequency detector (18) capable of outputting up and down signals to a charge pump (22) through separate signal paths (24, 26) and a phase lock detector (34) coupled to receive the up and down signals. The phase lock detector (34) determines the difference between the up and down signals from the phase/frequency detector (18) and in response generates a phase lock indicator signal PLL.sub.-- OUT.

Abstract: A field-programmable gate array device (FPGA) having plural rows and columns of logic function units is organized with symmetrical and complementary Variable Grain Architecture (VGA) and Variable Length Interconnect Architecture (VLI). Synthesis mapping exploits the diversified and symmetric resources of the VGA and VLI to efficiently pack function development into logic units of matched granularity and to transfer signals between logic units with interconnect lines of minimal length.

Abstract: A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes plural columns of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each logic function unit (VGB) is organized to process a nibble of data. Each embedded memory block is multi-ported and organized to store addressable nibbles of data. Interconnect resources are provided for efficiently transferring nibbles of data between the logic function units (VGB's) and corresponding memory blocks. Further interconnect resources (SVIC's) are provided for supplying address and control signals to each memory block. In one embodiment each memory block has at least one read-only port and at least one read/write port that are individually addressable and individually switchable into high output impedance tri-state modes.

Abstract: A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. A selector is provided with each of peripherally distributed IOB's of each row or column for selecting an output signal from plural one of long lines that extend perpendicularly relative to the peripheral boundary at which the IOB resides.

Abstract: A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block).

Abstract: A first and second multiplexer is coupled to a first and second inter-connect channel for providing control and timing signals to the plurality of IOBs.

Abstract: An in-system programmable and verifiable (ISPAV) configuration restoring device (CROP device) has an Electrically Erasable and reprogrammable, NonVolatile Integrated Storage array (e.g., a FLASH EE.sub.-- NVIS array) into which configuration instructions may be written for later readout during configuration restoration of a Programmable Logic Device (PLD) where the PLD has a volatile configuration memory. The volatile PLD may be an FPGA or a CPLD. The ISPAV CROP device includes a shared shift register through which configuration instructions read from the EE.sub.-- NVIS array are serially shifted out to a to-be-configured PLD. The shared shift register is also used for loading new configuration instructions into the EE.sub.-- NVIS array by way of a 4-wire interface such as JTAG and also for verifying proper writing of these instructions into the EE.sub.-- NVIS array.

Abstract: A Variable Grain Architecture (VGA) includes a shared output component (SOC) that may be used for outputting different signals onto a shared longline within an FPGA. Plural VGB's make shared use of the SOC to out respective function signals to the shared longline.

Abstract: A serial scan chain extends into an array of SRAM cells within a multi-ported memory system for allowing serial introduction of write data into the SRAM cells and serial read-back of the data. Initial data may be pre-loaded into the SRAM cells by way of the serial scan chain before being read parallel-wise in response to read requests submitted through any of multiple, parallel data access ports of the system.

Abstract: An improved EEPROM cell having a field-edgeless tunnel window is provided which is fabricated by a STI process so as to produce reliable endurance and data retention. The EEPROM cell includes a floating gate, a programmable junction region, and a tunneling oxide layer separating the programmable junction region and the floating gate. The tunneling oxide layer defines a tunnel window which allows for programming and erasing of the floating gate by tunneling electrons therethrough. The programmable junction region has a width dimension and a length dimension so as to define a first area. The tunnel window has a width dimension and a length dimension so as to define a second area. The second area of the tunnel window is completely confined within the first area of the programmable junction region so as to form a field-edgeless tunnel window.

Abstract: Electrostatic discharge (ESD) protection is provided for NMOS pull up transistors 700A-H and 702A-H of a 5.0 volt compatible output buffer using 2.5 volt process transistors. The ESD protection includes a p+ guard ring region 901-903 surrounding each pair of NMOS pull up transistors such as 700A, 702A. The p+ guard ring enables pull up of the p- epitaxical region supporting the NMOS pull up transistors during an ESD event. With a first set of series connected NMOS transistors turning on during an ESD event, its surrounding p+ guard ring will pull up the p- epitaxical region around other sets of series connected NMOS transistors to prevent secondary breakdown in the first NMOS pair. Further, ballast resistors 701A-H and 703A-H are included to separate individual pairs of NMOS pull up transistors 700A-H and 702A-H from the pad and from a power supply connection NV3.

Abstract: A method for sorting semiconductor devices having a plurality of non-volatile memory cells effectively screens memory cells with a predicted lifetime less than a desired lifetime, in part, by determining a minimum acceptable voltage value and a maximum acceptable voltage drop value for each cell in the device at a margin sort read point. In the method of the invention, the device is first stressed by programming and erasing the memory cells for a predetermined number of cycles. After stressing the device, the device is erased and an initial voltage across a floating-gate is measured at time=0. The initial voltage value is compared with acceptable minimum and maximum initial voltages. The device is discarded if the initial voltage value is outside of the range defined by the minimum and maximum initial voltages. Next, the device is baked at a predetermined temperature. Then, a voltage drop value is determined by measuring a second voltage on the floating-gate at the margin sort read point.