Patents Assigned to Varian Semiconductor Equipment Associates, Inc.
  • Publication number: 20210111031
    Abstract: A method may include forming in a substrate a first array of a first material of first linear structures, interspersed with a second array of a second material, of second linear structures, the first and second linear structures elongated along a first axis. The method may include generating a chop pattern in the first layer, comprising a third linear array, interspersed with a fourth linear array. The third and fourth linear arrays may be elongated along a second axis, forming a non-zero angle of incidence with respect to the first axis. The third linear array may include alternating portions of the first and second material, while the fourth linear array comprises an array of cavities, arranged within the patterning layer. The method may include elongating a first set of cavities along the first axis, to form a first set of elongated cavities bounded by the first material.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Sony Varghese
  • Patent number: 10974276
    Abstract: A system that reduces the amount of water that enters a process chamber via a movable shaft is disclosed. The surface of the shaft is made hydrophobic. Any water droplets that are collected on the hydrophobic shaft are disposed at a high contact angle, making it more likely that these water droplets fall from the shaft. Further, any water that enters the process chamber is more readily removed from the shaft due to the lower energy of liberation. Reducing the amount of water in a process chamber may improve the lifetime of the components in the process chamber and may improve the yield of the workpieces being processed. This may be especially relevant when process gasses that contain halogens are employed.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: April 13, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ernest E. Allen, Jr., Jonathan David Fischer, Jeffrey E. Krampert
  • Patent number: 10971403
    Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: April 6, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
  • Patent number: 10971368
    Abstract: A method of treating a substrate includes directing ions to the substrate along at least one non-zero angle with respect to a perpendicular to a substrate surface in a presence of a reactive ambient containing a reactive species where the substrate includes a surface feature. At least one surface of the surface feature is etched using the ions in combination with the reactive ambient at a first etch rate that is greater than a second etch rate when the ions are directed to the substrate without the reactive ambient and greater than a third etch rate when the reactive ambient is provided to the substrate without the ions.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: April 6, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Steven R. Sherman, Simon Ruffell, John Hautala, Adam Brand
  • Patent number: 10971926
    Abstract: An apparatus for controlling and monitoring the lifetime of a superconducting fault current limiter. The apparatus may include a processor; and a memory unit coupled to the processor, including a lifetime routine, where the lifetime routine is operative on the processor to monitor the superconducting fault current limiter. The lifetime routine may include a lifetime estimation processor to receive a set of fault information for a fault event of a superconductor tape of the superconducting fault current limiter, determine a present state of the superconductor tape based upon the set of fault information, and determine an estimated lifetime of the superconductor tape based upon the present state. The present state may be determined from additional information such as fault history on the superconducting fault current limiter, as well as a database of superconductor tape behavior with respect to various faults.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: April 6, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Saeed Jazebi, John Evans
  • Patent number: 10937663
    Abstract: Disclosed are methods for removing bridge defects using an angled implant and selective photoresist etch. In one embodiment, a method includes providing a semiconductor device including plurality of photoresist lines on a stack of layers, wherein a bridge defect extends between two or more photoresist lines of the plurality of photoresist lines. The method may further include implanting a sidewall and an upper surface of the two or more photoresist lines with an ion beam disposed at an angle, the angle being a non-zero angle of inclination with respect to a perpendicular to a plane of the upper surface of the stack of layers. The method may further include etching the semiconductor device to remove the bridge defect.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: March 2, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tristan Y. Ma, Juiyuan Hsu
  • Patent number: 10903082
    Abstract: A method may include forming in a substrate a first array of a first material of first linear structures, interspersed with a second array of a second material, of second linear structures, the first and second linear structures elongated along a first axis. The method may include generating a chop pattern in the first layer, comprising a third linear array, interspersed with a fourth linear array. The third and fourth linear arrays may be elongated along a second axis, forming a non-zero angle of incidence with respect to the first axis. The third linear array may include alternating portions of the first and second material, while the fourth linear array comprises an array of cavities, arranged within the patterning layer. The method may include elongating a first set of cavities along the first axis, to form a first set of elongated cavities bounded by the first material.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: January 26, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Sony Varghese
  • Patent number: 10903096
    Abstract: Provided herein are approaches for cooling a process chamber window. In some embodiments, a system for process chamber window cooling may include a process chamber for processing a wafer, wherein the process chamber includes a window. In some embodiments, the window allows light from a lamp assembly to be delivered to the wafer. The system further includes a cooling apparatus operable with the process chamber, the cooling apparatus for delivering a gas to the window. The cooling apparatus includes a support ring supporting the window. The support ring includes a perimeter wall, and a plurality of slots formed through the perimeter wall. The plurality of slots may deliver a gas (e.g., air) across the window.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: January 26, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Paul E. Pergande, James D. Strassner
  • Publication number: 20210013001
    Abstract: Provided herein are approaches for in-situ plasma cleaning of ion beam optics. In one approach, a system includes a component (e.g., a beam-line component) of an ion implanter processing chamber. The system further includes a power supply for supplying a first voltage and first current to the component during a processing mode and a second voltage and second current to the component during a cleaning mode. The second voltage and current are applied to one or more conductive beam optics of the component, individually, to selectively generate plasma around one or more of the one or more conductive beam optics. The system may further include a flow controller for adjusting an injection rate of an etchant gas supplied to the beam-line component, and a vacuum pump for adjusting pressure of an environment of the beam-line component.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kevin Anglin, William Davis Lee, Peter Kurunczi, Ryan Downey, Jay T. Scheuer, Alexandre Likhanskii, William M. Holber
  • Patent number: 10892136
    Abstract: A system for reducing clogging and deposition of feed gas on a gas tube entering an ion source chamber is disclosed. To lower the overall temperature of the gas tube, a gas bushing, made of a thermally isolating material, is disposed between the ion source chamber and the gas tube. The gas bushing is made of a thermally isolating material, such as titanium, quartz, boron nitride, zirconia or ceramic. The gas bushing has an inner channel in fluid communication with the ion source chamber and the gas tube to allow the flow of feed gas to the ion source chamber. The gas bushing may have a shape that is symmetrical, allowing it to be flipped to extend its useful life. In some embodiments, the gas tube may be in communication with a heat sink to maintain its temperature.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: January 12, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Craig R. Chaney, Adam M. McLaughlin
  • Publication number: 20210005461
    Abstract: An optical grating component may include a substrate, and an optical grating, the optical grating being disposed on the substrate. The optical grating may include a plurality of angled structures, disposed at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate, wherein the plurality of angled structures are arranged to define a variable depth along a first direction, the first direction being parallel to the plane of the substrate.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 7, 2021
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: John Hautala, Morgan Evans, Rutger Meyer Timmerman Thijssen, Joseph C. Olson
  • Patent number: 10886279
    Abstract: A memory device may include an active device region, disposed at least partially in a first level. The memory device may include a storage capacitor, disposed at least partially in a second level, above the first level, wherein the first level and the second level are parallel to a substrate plane. The memory device may also include a contact via, the contact via extending between the storage capacitor and the active device region, and defining a non-zero angle of inclination with respect to a perpendicular to the substrate plane.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 5, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Sony Varghese, Anthony Renau, Morgan Evans, John Hautala, Joe Olson
  • Patent number: 10879055
    Abstract: A method is provided. The method may include providing a substrate, the substrate comprising a substrate surface, the substrate surface having a three-dimensional shape. The method may further include directing a depositing species from a deposition source to the substrate surface, wherein a layer is deposited on a deposition region of the substrate surface. The method may include performing a substrate scan during the directing or after the directing to transport the substrate from a first position to a second position. The method may also include directing angled ions to the substrate surface, in a presence of the layer, wherein the layer is sputter-etched from a first portion of the deposition region, and wherein the layer remains in a second portion of the deposition region.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 29, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher Hatem, Kevin Anglin
  • Publication number: 20200399758
    Abstract: An apparatus for controlling precursor flow. The apparatus may include a processor; and a memory unit coupled to the processor, including a flux control routine. The flux control routine may be operative on the processor to monitor the precursor flow and may include a flux calculation processor to determine a precursor flux value based upon a change in detected signal intensity received from a cell of a gas delivery system to deliver a precursor.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Elaina Babayan, Sarah White, Vijay Venugopal, Jonathan Bakke
  • Publication number: 20200391251
    Abstract: A cleaning tool for cleaning a glass surface of an accelerator column is disclosed. The cleaning tool includes a shaft including a first end and a second end; a foam body located at the first end of the shaft; and a mounting bracket coupled to the first end of the shaft, the mounting bracket receiving the foam body. An outer circumference of the foam body includes a textured cleaning surface for contacting the glass surface of the accelerator column.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 17, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Michael J. Blanchard, Nevin H. Clay, Joshua R. Conahan, Christopher Lupoli
  • Patent number: 10867772
    Abstract: Provided herein are approaches for increasing surface area of a conductive beam optic by providing grooves or surface features thereon. In one approach, the conductive beam optic may be part of an electrostatic filter having a plurality of conductive beam optics disposed along an ion beam-line, wherein at least one conductive beam optic includes a plurality of grooves formed in an exterior surface. In some approaches, a power supply may be provided in communication with the plurality of conductive beam optics, wherein the power supply is configured to supply a voltage and a current to the plurality of conductive beam optics. The plurality of grooves may be provided in a spiral pattern along a length of the conductive beam optic, and/or oriented parallel to a lengthwise axis of the conductive beam optic.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: December 15, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Eric Hermanson, Philip Layne, James Alan Pixley
  • Patent number: 10867773
    Abstract: An apparatus may include a first grounded drift tube, arranged to accept a continuous ion beam, at least two AC drift tubes, arranged in series, downstream to the first grounded drift tube, and a second grounded drift tube, downstream to the at least two AC drift tubes. The apparatus may include an AC voltage assembly, electrically coupled to at least two AC drift tubes. The AC voltage assembly may include a first AC voltage source, coupled to deliver a first AC voltage signal at a first frequency to a first AC drift tube of at least two AC drift tubes. The AC voltage assembly may further include a second AC voltage source, coupled to deliver a second AC voltage signal at a second frequency to a second AC drift tube of the at least two AC drift tubes, wherein the second frequency comprises an integral multiple of the first frequency.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: December 15, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Frank Sinclair
  • Patent number: 10847971
    Abstract: Embodiments of the disclosure include a fault current limiter having a first current splitting device including a primary winding and secondary winding wound around a first core, and a second current splitting device including a primary winding and a secondary winding wound around a second core. The fault current limiter may further include a fault current limiter module (e.g., a switching module) electrically connected in series between the secondary winding of the first current splitting device and the secondary winding of the second current splitting device. The fault current limiter may further include a second fault current limiter module electrically connected in series with the secondary winding of the second current splitting device. By splitting the fault current limiter into parts with fault current limiter modules interspersed between the windings, the fault current limiter may be to be built with less insulation between the windings.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: November 24, 2020
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Adrian Wilson, Shankar Kodle, Saeed Jazebi, Piotr Lubicki
  • Patent number: 10847372
    Abstract: Methods for processing of a workpiece are disclosed. The actual rate at which different portions of an ion beam can process a workpiece, referred to as the processing rate profile, is determined by measuring the amount of material removed from, or added to, a workpiece by the ion beam as a function of ion beam position. An initial thickness profile of a workpiece to be processed is determined. Based on the initial thickness profile, a target thickness profile, and the processing rate profile of the ion beam, a first set of processing parameters are determined. The workpiece is then processed using this first set of processing parameters. In some embodiments, an updated thickness profile is determined after the first process and a second set of processing parameters are determined. A second process is performed using the second set of processing parameters. Optimizations to improve throughput are also disclosed.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: November 24, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan D. Evans, Kevin Anglin, Ross Bandy
  • Publication number: 20200357603
    Abstract: An ion implantation system, including an ion source, and a buncher to receive a continuous ion beam from the ion source, and output a bunched ion beam. The buncher may include a drift tube assembly, having an alternating sequence of grounded drift tubes and AC drift tubes. The drift tube assembly may include a first grounded drift tube, arranged to accept a continuous ion beam, at least two AC drift tubes downstream to the first grounded drift tube, a second grounded drift tube, downstream to the at least two AC drift tubes. The ion implantation system may include an AC voltage assembly, coupled to the at least two AC drift tubes, and comprising at least two AC voltage sources, separately coupled to the at least two AC drift tubes. The ion implantation system may include a linear accelerator, comprising a plurality of acceleration stages, disposed downstream of the buncher.
    Type: Application
    Filed: July 14, 2020
    Publication date: November 12, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Frank Sinclair