Patents Assigned to Varian Semiconductor Equipment Associates, Inc.
  • Publication number: 20200233125
    Abstract: Embodiments herein provide systems and methods for forming an optical component. A method may include providing a plurality of proximity masks between a plasma source and a workpiece, the workpiece including a plurality of substrates secured thereto. Each of the plurality of substrates may include first and second target areas. The method may further include delivering, from the plasma source, an angled ion beam towards the workpiece, wherein the angled ion beam is then received at one of the plurality of masks. A first proximity mask may include a first set of openings permitting the angled ion beam to pass therethrough to just the first target area of each of the plurality of substrates. A second proximity mask may include a second set of openings permitting the angled ion beam to pass therethrough just to the second target area of each of the plurality of substrates.
    Type: Application
    Filed: February 9, 2020
    Publication date: July 23, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan Evans, Rutger Meyer Timmerman Thijssen, Joseph Olson, Peter Kurunczi, Robert Masci
  • Patent number: 10720357
    Abstract: A method of forming a semiconductor device. The method may include providing a device structure, where the device structure comprises a masked portion and a cut portion. The masked portion may comprise a mask covering at least one semiconductor fin of a fin array, and the cut portion may comprise a trench, where the trench exposes a semiconductor fin region of the fin array. The method may further include providing an exposure of the trench to oxidizing ions, the oxidizing ions to transform a semiconductor material into an oxide.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 21, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Naushad K Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee, Jun Lee
  • Patent number: 10714301
    Abstract: Provided herein are approaches for reducing particles in an ion implanter. An electrostatic filter may include a housing and a plurality of conductive beam optics within the housing. The conductive beam optics are arranged around an ion beam-line directed towards a wafer, and may include entrance aperture electrodes proximate an entrance aperture of the housing. The conductive beam optics may further include energetic electrodes downstream along the ion beam-line from the entrance aperture electrodes, and ground electrodes downstream from the energetic electrodes. The energetic electrodes are positioned farther away from the ion beam-line than the entrance electrodes and the ground electrodes, thus causing the energetic electrodes to be physically blocked from impact by an envelope of back-sputter material returning from the wafer. The electrostatic filter may further include an electrical system for independently delivering a voltage and a current to each of the conductive beam optics.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: July 14, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Shengwu Chang, Frank Sinclair, Alexandre Likhanskii, Christopher Campbell, Robert C. Lindberg
  • Patent number: 10707050
    Abstract: A glitch monitoring system is disclosed. The glitch monitoring system allows the capture of voltage and current data from one or more channels. Additionally, voltage and current data that occurred prior to the glitch can also be captured for further analysis. The amount of data may be thousands or millions of bytes. Additionally, the description of a glitch, including an upper threshold, a lower threshold and a duration, can be programmed. This allows spurious perturbation in voltage or current to be ignored if desired. Further, the voltage and current data may be filtered if desired prior to being stored in memory. This data can later be retried by a main controller and analyzed to determine a potential cause of the glitch and potential remedial actions.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 7, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Keith E. Kowal
  • Patent number: 10704693
    Abstract: A rotary union that includes a heated ferrofluid seal is disclosed. The rotary union includes an inner rotating shaft, an intermediate rotating shaft and an outer rotating shaft. The inner rotating shaft is hollow to allow the flow of cryogenic fluid in one direction. The inner rotating shaft and the intermediate shaft are spaced apart to create a channel for the return of the cryogenic fluid. The intermediate rotating shaft is separated from the outer rotating shaft by a gap so as to reduce thermal conductivity. In this way, the temperature of the outer rotating shaft is greater than the temperature of the cryogenic fluid. A heated ferrofluid seal is disposed between the outer rotating shaft and the housing.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 7, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Robert Mitchell, Roger B. Fish, Shardul S. Patel
  • Patent number: 10692697
    Abstract: An ion implantation system may include an ion source to generate an ion beam, a substrate stage disposed downstream of the ion source; and a deceleration stage including a component to deflect the ion beam, where the deceleration stage is disposed between the ion source and substrate stage. The ion implantation system may further include a hydrogen source to provide hydrogen gas to the deceleration stage, wherein energetic neutrals generated from the ion beam are not scattered to the substrate stage.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: June 23, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Frank Sinclair, Daniel Tieger, Klaus Becker
  • Patent number: 10692872
    Abstract: A memory device may include an active device region, disposed at least partially in a first level. The memory device may include a storage capacitor, disposed at least partially in a second level, above the first level, wherein the first level and the second level are parallel to a substrate plane. The memory device may also include a contact via, the contact via extending between the storage capacitor and the active device region, and defining a non-zero angle of inclination with respect to a perpendicular to the substrate plane.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 23, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Sony Varghese, Anthony Renau, Morgan Evans, John Hautala, Joe Olson
  • Patent number: 10685865
    Abstract: A method of forming a semiconductor device may include providing a semiconductor device structure. The semiconductor device structure may include semiconductor fins pitched at a fin pitch on a substrate and a mask, disposed over the semiconductor fins, the mask defining a plurality of openings. The semiconductor device structure may further include an isolation oxide disposed on the substrate, between the semiconductor fins. The method may further include directing angled ions into the at least one of the plurality of openings. The angled ions may form at least one trench between at least one pair of the semiconductor fins, in the substrate below the isolation oxide between the at least one pair of the semiconductor fins. Furthermore, a width within the substrate of the at least one trench is greater than a minimum fin pitch and greater than a width of the at least one trench above the substrate.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 16, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Sony Varghese, Johannes Van Meer, John Hautala
  • Patent number: 10672634
    Abstract: The present disclosure describes a method and apparatus for determining whether components in a semiconductor manufacturing system are authorized for use in that system. By embedding an identification feature in the component, it is possible for a controller to determine whether that component is qualified for use in the system. Upon detection of an unauthorized component, the system may alert the user or, in certain embodiments, stop operating of the system. This identification feature is embedded in a component by using an additive manufacturing process that allows the identification feature to be embedded in the component without subjecting the identification feature to extreme temperatures.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: June 2, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Craig R. Chaney, Adam M. McLaughlin
  • Patent number: 10669430
    Abstract: A workpiece support, such as an end effector, is coated on at least one of its surfaces with an anti-reflective material. The anti-reflective material improves the transmission of light through the workpiece support. The workpiece support may be disposed in a chamber, with heating elements disposed beneath the workpiece support, such that the workpiece support is disposed between the heating elements and the workpiece. In certain embodiments, the heating elements may be LEDs or tungsten halogen lamps. The anti-reflective material allows more efficient energy transfer from the heating elements to the workpiece. This may result in improved temperature uniformity across the workpiece. The anti-reflective material may be magnesium fluoride or a multi-layer optical coating. Alternatively, the heating elements may be disposed above the workpiece. In this case, the reduced reflection from the workpiece support may minimize the temperature increase on the portion of the workpiece disposed above the workpiece support.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 2, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Paul E. Pergande
  • Publication number: 20200168612
    Abstract: A method may include providing a substrate, the substrate comprising a substrate base and a patterning stack, disposed on the substrate base. The substrate may include first linear structures in the patterning stack, the first linear structures being elongated along a first direction; and second linear structures in the patterning stack, the second linear structures being elongated along a second direction, the second direction forming a non-zero angle with respect to the first direction. The method may also include selectively forming a set of sidewall spacers on one set of sidewalls of the second linear structures.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 28, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Sony Varghese, Naushad Variam
  • Publication number: 20200166681
    Abstract: Embodiments herein provide systems and methods for forming an optical component. A method may include providing a plurality of proximity masks between a plasma source and a workpiece, the workpiece including a plurality of substrates secured thereto. Each of the plurality of substrates may include first and second target areas. The method may further include delivering, from the plasma source, an angled ion beam towards the workpiece, wherein the angled ion beam is then received at one of the plurality of masks. A first proximity mask may include a first set of openings permitting the angled ion beam to pass therethrough to just the first target area of each of the plurality of substrates. A second proximity mask may include a second set of openings permitting the angled ion beam to pass therethrough just to the second target area of each of the plurality of substrates.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 28, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan Evans, Rutger Meyer Timmerman Thijssen, Joseph Olson, Peter Kurunczi, Robert Masci
  • Patent number: 10665433
    Abstract: A workpiece processing apparatus allowing independent control of the voltage applied to the shield ring and the workpiece is disclosed. The workpiece processing apparatus includes a platen. The platen includes a dielectric material on which a workpiece is disposed. A bias electrode is disposed beneath the dielectric material. A shield ring, which is constructed from a metal, ceramic, semiconductor or dielectric material, is arranged around the perimeter of the workpiece. A ring electrode is disposed beneath the shield ring. The ring electrode and the bias electrode may be separately powered. This allows the surface voltage of the shield ring to match that of the workpiece, which causes the plasma sheath to be flat. Additionally, the voltage applied to the shield ring may be made different from that of the workpiece to compensate for mismatches in geometries. This improves uniformity of incident angles along the outer edge of the workpiece.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 26, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Alexandre Likhanskii, Maureen Petterson, John Hautala, Anthony Renau, Christopher A. Rowland, Costel Biloiu
  • Patent number: 10658207
    Abstract: Techniques for reducing particle contamination on a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a platen having different regions, where the pressure levels in the regions may be substantially equal. For example, the platen may comprise a platen body comprising first and second recesses, the first recess defining a fluid region for holding fluid for maintaining a temperature of the substrate at a desired temperature, the second recess defining a first cavity for holding a ground circuit; a first via defined in the platen body, the first via having first and second openings, the first opening proximate to the fluid region and the second opening proximate to the first cavity, wherein pressure level of the fluid region may be maintained at a level that is substantially equal to pressure level of the first cavity.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: May 19, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: David E. Suuronen, Dale K. Stone, Shigeo Oshiro, Arthur P. Riaf, Edward D. MacIntosh
  • Publication number: 20200152466
    Abstract: A method of doping a substrate. The method may include providing a substrate in a process chamber. The substrate may include a semiconductor structure, and a dopant layer disposed on a surface of the semiconductor structure. The method may include maintaining the substrate at a first temperature for a first interval, the first temperature corresponding to a vaporization temperature of the dopant layer. The method may further include rapidly cooling the substrate to a second temperature, less than the first temperature, and heating the substrate from the second temperature to a third temperature, greater than the first temperature.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Piero Sferlazzo, Roger Fish, Dale K. Stone
  • Patent number: 10651011
    Abstract: An apparatus may include a first grounded drift tube, arranged to accept a continuous ion beam, at least two AC drift tubes, arranged in series, downstream to the first grounded drift tube, and a second grounded drift tube, downstream to the at least two AC drift tubes. The apparatus may include an AC voltage assembly, electrically coupled to at least two AC drift tubes. The AC voltage assembly may include a first AC voltage source, coupled to deliver a first AC voltage signal at a first frequency to a first AC drift tube of at least two AC drift tubes. The AC voltage assembly may further include a second AC voltage source, coupled to deliver a second AC voltage signal at a second frequency to a second AC drift tube of the at least two AC drift tubes, wherein the second frequency comprises an integral multiple of the first frequency.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 12, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Frank Sinclair
  • Patent number: 10643823
    Abstract: Disclosed is a semiconductor processing apparatus including one or more components having a conductive or nonconductive foam material. In some embodiments, the component is a plasma flood gun including a shield assembly coupled to the plasma flood gun. The shield assembly may include a first shield having a first main side facing an ion beam target, and a connection block coupled to a second main side of the first shield. The shield assembly may further include a mounting plate coupled to the connection block, and a second shield coupled to the mounting plate by a bracket. In some embodiments, the first shield and/or one or more process chamber walls includes a foam material, such as a conductive or nonconductive foam.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: May 5, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: James Alan Pixley, Eric D. Hermanson, Philip Layne, Lyudmila Stone, Thomas Stacy
  • Patent number: 10644117
    Abstract: A method may include providing a device structure, where the device structure includes a semiconductor region, and a gate structure, disposed over the semiconductor region. The gate structure may further include a gate metal. The method may further include oxidizing an upper portion of the gate metal, wherein the upper portion forms an oxide cap, and wherein a lower portion of the gate metal remains metallic.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: May 5, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Wenhui Wang, Jun Lee, Sony Varghese
  • Publication number: 20200135573
    Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.
    Type: Application
    Filed: December 13, 2019
    Publication date: April 30, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
  • Patent number: 10633743
    Abstract: A system and method for removing metal from a substrate in a controlled manner is disclosed. The system includes a chamber, with one or more gas inlets to allow the flow of gasses into the chamber, at least one exhaust pump, to exhaust gasses from the chamber, and a heater, capable of modifying the temperature of the chamber. In some embodiments, one or more gasses are introduced into the chamber at a first temperature. The atoms in these gasses chemically react with the metal on the surface of the substrate to form a removable compound. The gasses are then exhausted from the chamber, leaving the removable compound on the surface of the substrate. The temperature of the chamber is then elevated to a second temperature, greater than the sublimation temperature of the removable compound. This increased temperature allows the removable compound to become gaseous and be exhausted from the chamber.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: April 28, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tsung-Liang Chen, Benjamin Schmiege, Jeffrey W. Anthis, Glen Gilchrist