Patents Assigned to Verisilicon
  • Patent number: 11950066
    Abstract: The present disclosure provides a TWS earphone interaction method and system, and TWS earphones. When a main earphone and a secondary earphone receive a data packet sent by an audio source, within a residual slot of a data transmission slot, the main earphone and the secondary earphone can perform data interaction, wherein the residual slot is the remaining data transmission slot after the data packet is transmitted. When a data packet is received, the main earphone sends acknowledgment information to the audio source, within a residual slot of a next data transmission slot, the main earphone and the secondary earphone can perform data interaction, wherein the residual slot is the remaining of the next data transmission slot after the acknowledgment information is sent.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: April 2, 2024
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventor: Maogang Li
  • Patent number: 11928470
    Abstract: Introduced herein is a program counter advancing technique that uses NOP padding without its limitations. During a build process, the introduced technique removes EOG markers for instruction groups that are immediately followed by the NOP instructions that are immediately followed by an instruction group beginning at a start of a cache line. As such, during an execution process, when the processing unit detects an absence of an EOG marker in the requested instruction group, it knows that a group of NOP instructions are about to follow and skips over them by directly advancing the program counter to a start of a subsequent cache line where the next instruction group starts. In addition to the presence of an EOG marker, the introduced technique also takes into account whether the requested instruction group is a straddling group when advancing the program counter to a start of the subsequent cache line.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: March 12, 2024
    Assignee: VeriSilicon Holdings Co., Ltd.
    Inventor: Tracy T. Nguyen
  • Patent number: 11783513
    Abstract: The present disclosure provides a vector graphics data processing method, system, medium, and vector graphics processing device. The method includes the following operations: building a vector primitive path intersection data structure (PIDS) based on coordinates of path intersections (PIs); when a new PI is generated, comparing information of the new PI to information of existing PIs corresponding to an X coordinate or Y coordinate of the new PI; and storing the information of the new PI at a corresponding position in the PIDS corresponding to the X coordinate or Y coordinate of the new PI based on a result of the comparing. Only effective PI data are saved, thereby reducing memory footprint and memory bandwidth, and improving vector graphics processing performance.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: October 10, 2023
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.
    Inventors: Mike M Cai, Yi Zhang, Yijun Li, Kui Qin
  • Publication number: 20230262210
    Abstract: A data compression method is provided for compressing an image. A coding module may select a plurality of pixels with a sequence order from the image, and compress the plurality of pixels to generate a plurality of compressed pixels. For a current pixel p[i] having a previous pixel p[i?1] and a next pixel p[i+1], the coding module generates a coding mode M[i+1] configured for compressing the p[i+1], and generates a fixed-rate compressed value c[i] corresponding to the p[i]. The coding module stores the c[i] in a compressed pixel, and c[i] encapsulates the coding mode M[i+1]. The coding module then stores the plurality of compressed pixels into a compressed image corresponding to the image.
    Type: Application
    Filed: January 30, 2023
    Publication date: August 17, 2023
    Applicant: VeriSilicon Holdings Co., Ltd.
    Inventors: Lefan ZHONG, Mankit LO, Wei MIAO
  • Patent number: 11693820
    Abstract: The present disclosure provides a cooperative access method, system, and architecture of an external storage.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: July 4, 2023
    Assignees: VeriSilicon Microelectronics (Chengdu) Co., Ltd., VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.
    Inventor: Yongliang Li
  • Patent number: 11647322
    Abstract: The present disclosure provides a TWS earphone communication method and system, and TWS earphones. The method includes: when an audio source sends a data packet and a main earphone correctly receives the data packet, the main earphone sends acknowledgment information in an acknowledgment information slot; when the data packet is incorrectly received by the main earphone, no information is sent in the acknowledgment information slot; and when the data packet is received correctly by a secondary earphone, the secondary earphone does not send any information in the acknowledgment information slot. When the data packet is not received correctly by the secondary earphone, it sends interference information in the acknowledgment information slot.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: May 9, 2023
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Shuai Li, Maogang Li
  • Patent number: 11599334
    Abstract: A device for performing multiply/accumulate operations processes values in first and second buffers and having a first width using a computational pipeline with a second width, such as half the first width. A sequencer processes combinations of portions (high-high, low-low, high-low, low-high) of the values in the first and second buffers using a multiply/accumulate circuit and adds the accumulated result of each combination of portions to a group accumulator. Adding to the group accumulator may be preceded by left shifting the accumulated result (the first width for the high-high combination and the second width for the low-high and high-low combination).
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: March 7, 2023
    Assignees: VeriSilicon Microelectronics, VeriSilicon Holdings Co., Ltd.
    Inventors: Mankit Lo, Meng Yue, Jin Zhang
  • Patent number: 11600243
    Abstract: A display controller, comprising a 3D_LUT random access memory, which stores at least a 3D Lookup table; and a display control processing unit, comprising: a computing unit, a register, a color signal booster, and a color signal attenuator; wherein after input color signals are received by the color signal booster, and the color signal booster amplifies color signals by a first predetermined factor, wherein the computing unit calculates the address of the 3D Lookup table, and loads the 3D Lookup table from the 3D_LUT random access memory according to the register, wherein the color signal attenuator attenuates color signals by a second predetermined factor. The present disclosure significantly increases the precision of color conversion from one RGB color space to another RGB color space, and does not increase the RAM cost, since the cost of multiplying or dividing by power of 2, for example, is limited.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: March 7, 2023
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Lefan Zhong, Song Li, Jun Chen, Isaac Wang
  • Patent number: 11563407
    Abstract: The present disclosure provides a mixing circuit with high harmonic suppression ratio, including: a multi-phase generation module, which receives a first input signal and generates eight first square wave signals with a phase difference of 45°; a quadrature phase generation module, which receives a second input signal and generates four second square wave signals with a phase difference of 90°; a harmonic suppression module, connected with an output end of the quadrature phase generation module to filter out higher order harmonic components in the second square wave signals; and a mixing module, connected with output ends of the multi-phase generation module and the harmonic suppression module to mix output signals of the multi-phase generation module and the harmonic suppression module. The mixing circuit with high harmonic suppression ratio adds a harmonic suppression module on the basis of multi-phase mixing, thereby improving the harmonic suppression ratio of the output signal.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 24, 2023
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Yu Li, Peng Ma, Yi Zeng, Shenglei Wang, Tony Qian
  • Patent number: 11557090
    Abstract: The present disclosure provides a tessellation data processing method, system, medium and vector graphics processing device. The method includes: constructing a data structure including a content table and information tables in memory; when a vector line generated by tessellation intersects an horizontal/vertical line to obtain a new intersection, reading an address and number of Xnodes or Ynodes of an information table in the content table corresponding to a row/column corresponding to the Y/X coordinate of the intersection; according to the address of the information table and the number of X/Ynodes of the information table, reading corresponding X/Ynodes from the memory; comparing information of the intersection with the X/Ynodes, and updating the X/Ynodes in the information table, or adding an X/Ynode to the information table at a position corresponding to the Y/X coordinates.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: January 17, 2023
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.
    Inventors: Cheng Chi, Jiangbo Li, Mike M Cai
  • Patent number: 11557091
    Abstract: The present disclosure provides a tessellation data processing method, system, media, and vector graphics processing device. The method includes: according to specified coordinates of intersections, creating different levels of cache tables, wherein the intersections result from vector lines generated by tessellation intersecting lines parallel to an x-axis or y-axis; storing in a content table addresses of information tables in memory, storing in a lowest level cache table an address of the content table in the memory, and storing an address of the lowest level cache table in the memory in a cache table one level higher than the lowest level cache table. The tessellation data processing method, system, media, and vector graphics processing device of the present disclosure store effective data in multi-level lookup tables based on coordinates of intersections, effectively reduce memory footprint, support multi-channel tessellation processing, and enhance the performance of vector graphics rendering.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: January 17, 2023
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.
    Inventors: Cheng Chi, Jiangbo Li, Mike M Cai
  • Patent number: 11546682
    Abstract: The present disclosure provides a method and system for synchronous audio playback of TWS earphones, The TWS earphones include a master earphone and a slave earphone; both the master earphone and the slave earphone include a first timer, a second timer, an audio DAC, and an audio playback phase-locked loop; the first timer and the second timer of the master earphone are respectively used to collect a real-time audio playback position of the master earphone and a public Bluetooth clock; the first timer and the second timer of the slave earphone are respectively used to collect a real-time audio playback position of the slave earphone and a local Bluetooth clock; the slave earphone calibrates audio data in the audio DAC, and the first timer and the audio playback phase-locked loop of the slave earphone, to achieve synchronization between the master earphone and the slave earphone.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: January 3, 2023
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventor: Shuai Li
  • Publication number: 20220342474
    Abstract: The present disclosure provides a method and system for controlling peak power consumption, which dynamically controls frequency by monitoring the load in real-time, thereby reducing the power consumption, and providing sufficient computing performance while controlling peak power consumption. The method and system for controlling peak power consumption of the present disclosure monitor the load in real-time, and reduce power consumption by dynamically and intelligently controlling the operating frequency, to achieve a balance between performance and power consumption, such that the chip works at the highest frequency when the peak power consumption does not exceed the load threshold, thereby effectively improving the work efficiency while achieving the power consumption control.
    Type: Application
    Filed: December 2, 2019
    Publication date: October 27, 2022
    Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.
    Inventor: Huiming ZHANG
  • Patent number: 11455781
    Abstract: The present disclosure provides a data reading/writing method and system for in 3D image processing, a storage medium and a terminal. The method includes the following steps: dividing a 3D image horizontally based on the vertical sliding technology, the 3D image is divided into at least two subimages, a processing data of each subimage is stored in a circular buffer, after the subimage is processed, an overlapping portion data required by next subimage is retained in the circular buffer; dividing a multi-layer network of an image processing algorithm into at least two segments, the data between adjacent layers in each segment only interact through buffer, not through DDR.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: September 27, 2022
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.
    Inventors: Zhonghao Cui, Mankit Lo, Ke Zhang, Huiming Zhang
  • Patent number: 11301214
    Abstract: A circuit for performing multiply/accumulate operations evaluates a type of each value of a pair of input values. Signed values are split into sign and magnitude. One or more pairs of arguments are input to a multiplier such that the arguments have fewer bits than the magnitude of signed values or unsigned values. This may include splitting input values into multiple arguments and inputting multiple pairs of arguments to the multiplier for a single pair of input values.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: April 12, 2022
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Mankit Lo, Meng Yue, Jin Zhang
  • Publication number: 20220058838
    Abstract: The present disclosure provides a vector graphics data processing method, system, medium, and vector graphics processing device. The method includes the following operations: building a vector primitive path intersection data structure (PIDS) based on coordinates of path intersections (PIs); when a new PI is generated, comparing information of the new PI to information of existing PIs corresponding to an X coordinate or Y coordinate of the new PI; and storing the information of the new PI at a corresponding position in the PIDS corresponding to the X coordinate or Y coordinate of the new PI based on a result of the comparing. Only effective PI data are saved, thereby reducing memory footprint and memory bandwidth, and improving vector graphics processing performance.
    Type: Application
    Filed: July 19, 2021
    Publication date: February 24, 2022
    Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.
    Inventors: Mike M CAI, Yi ZHANG, Yijun LI, Kui QIN
  • Publication number: 20220058867
    Abstract: The present disclosure provides a tessellation data processing method, system, media, and vector graphics processing device. The method includes: according to specified coordinates of intersections, creating different levels of cache tables, wherein the intersections result from vector lines generated by tessellation intersecting lines parallel to an x-axis or y-axis; storing in a content table addresses of information tables in memory, storing in a lowest level cache table an address of the content table in the memory, and storing an address of the lowest level cache table in the memory in a cache table one level higher than the lowest level cache table. The tessellation data processing method, system, media, and vector graphics processing device of the present disclosure store effective data in multi-level lookup tables based on coordinates of intersections, effectively reduce memory footprint, support multi-channel tessellation processing, and enhance the performance of vector graphics rendering.
    Type: Application
    Filed: July 19, 2021
    Publication date: February 24, 2022
    Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.
    Inventors: Cheng CHI, Jiangbo LI, Mike M CAI
  • Publication number: 20220051640
    Abstract: A display controller, comprising a 3D_LUT random access memory, which stores at least a 3D Lookup table; and a display control processing unit, comprising: a computing unit, a register, a color signal booster, and a color signal attenuator; wherein after input color signals are received by the color signal booster, and the color signal booster amplifies color signals by a first predetermined factor, wherein the computing unit calculates the address of the 3D Lookup table, and loads the 3D Lookup table from the 3D_LUT random access memory according to the register, wherein the color signal attenuator attenuates color signals by a second predetermined factor. The present disclosure significantly increases the precision of color conversion from one RGB color space to another RGB color space, and does not increase the RAM cost, since the cost of multiplying or dividing by power of 2, for example, is limited.
    Type: Application
    Filed: August 16, 2021
    Publication date: February 17, 2022
    Applicant: VeriSilicon Holdings Co., Ltd.
    Inventors: Lefan ZHONG, Song LI, Jun CHEN, Isaac WANG
  • Publication number: 20220028165
    Abstract: The present disclosure provides a tessellation data processing method, system, medium and vector graphics processing device. The method includes: constructing a data structure including a content table and information tables in memory; when a vector line generated by tessellation intersects an horizontal/vertical line to obtain a new intersection, reading an address and number of Xnodes or Ynodes of an information table in the content table corresponding to a row/column corresponding to the Y/X coordinate of the intersection; according to the address of the information table and the number of X/Ynodes of the information table, reading corresponding X/Ynodes from the memory; comparing information of the intersection with the X/Ynodes, and updating the X/Ynodes in the information table, or adding an X/Ynode to the information table at a position corresponding to the Y/X coordinates.
    Type: Application
    Filed: July 19, 2021
    Publication date: January 27, 2022
    Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.
    Inventors: Cheng Chi, Jiangbo Li, Mike M Cai
  • Publication number: 20220004522
    Abstract: The present disclosure provides a cooperative access method, system, and architecture of an external storage.
    Type: Application
    Filed: December 2, 2019
    Publication date: January 6, 2022
    Applicants: VeriSilicon Microelectronics (Chengdu) Co., Ltd., VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.
    Inventor: Yongliang LI