Abstract: A microphone array processing system and method carried out in the system. In one embodiment, the system includes: (1) a beamformer configured to perform adaptive beamforming on gain-compensated signals received from a plurality of microphones, the adaptive beamforming including dynamic range compression and diagonal loading of a sample correlation matrix based on order statistics and (2) a postfilter configured to receive an output of the beamformer and reduce noise components remaining from the beamforming.

Abstract: A prefetch buffer and prefetch method. In one embodiment, the prefetch buffer has a main buffer embodied as a direct-mapped cache, and the prefetch buffer includes: (1) an alias buffer associated with the main buffer and (2) a prefetch controller associated with the main buffer and the alias buffer and operable to cause the alias buffer to store potentially aliasing cachelines of a loop body instead of the main buffer.

Abstract: A circuit includes: a pull down circuit including a first PFET and a second PFET connected in series between a pad of a USB circuit and ground; and a pull up circuit including a first NFET and a second NFET connected in series between the pad and a supply voltage. The circuit includes: a third PFET connected to a gate of the first PFET and a gate of the second PFET; a third NFET connected to a gate of the first NFET and a gate of the second NFET; a fourth PFET connected to the first NFET and the second NFET; and a fourth NFET connected to the first PFET and the second PFET. A pad voltage has a nominal minimum and maximum. Each of the first PFET, the second PFET, the first NFET, and the second NFET has a nominal voltage less than the pad voltage nominal maximum.

Abstract: Search circuitry responsive to a single instruction for undertaking a step of a search of a data array for an extreme value therein, a method of searching a data array to identify an extreme value therein and a location thereof and a single-instruction, multiple-data (SIMD) processing unit incorporating the search circuitry or the method. In one embodiment, the search circuitry includes: a comparison element configured to compare two values in the data array, (2) multiplexers coupled to the comparison element and configured to select a more extreme value of the two values and a location in the data array of the more extreme value and (3) an incrementer configured to increment a counter associated with the search.

Abstract: A multiply-accumulate unit (MAU) configurable to perform both real and complex multiplication operations, a method of performing a mac operation and a processing unit incorporating the MAU or the method. In one embodiment, the MAU includes: (1) a first multiplier having a first vector input and a first scalar input and configured to multiply a first vector by a first scalar to yield a first product, (2) a second multiplier having a second vector input and a second scalar input and configured to multiply a second vector by a second scalar to yield a second product and (3) an accumulator coupled to the first multiplier and the second multiplier and configured to receive the first and second products.

Abstract: A microphone array processing system and method carried out in the system. In one embodiment, the system includes: (1) a beamformer configured to perform adaptive beamforming on gain-compensated signals received from a plurality of microphones, the adaptive beamforming including dynamic range compression and diagonal loading of a sample correlation matrix based on order statistics and (2) a postfilter configured to receive an output of the beamformer and reduce noise components remaining from the beamforming.

Abstract: The present invention provides for a security system for an electronic device that, in one embodiment, includes a processor with a software access key encrypted thereon and a software application with a processor access key encoded therein so that operation of the electronic device and execution of the software application requires both the software access key and the processor access key.

Abstract: A data processing element includes an input unit configured to provide instructions for scalar, vector and array processing, and a scalar processing unit configured to provide a scalar pipeline datapath for processing a scalar quantity. Additionally, the data processing element includes a vector processing unit coupled to the scalar processing unit and configured to provide a vector pipeline datapath employing a vector register for processing a one-dimensional vector quantity. The data processing element further includes an array processing unit coupled to the vector processing unit and configured to provide an array pipeline datapath employing a parallel processing structure for processing a two-dimensional vector quantity. A method of operating a data processing element and a MIMO receiver employing a data processing element are also provided.

Abstract: A signal decoder, a method of detecting an RF signal at a MIMO receiver and a MIMO receiver are disclosed herein. In one embodiment, the signal decoder includes: (1) a tree pruner configured to reduce a number of nodes of an MLD tree to expand based on modulation properties of the transmitted radio signals and SE enumeration of at least a portion of the MLD tree and (2) a vector sorter configured to sort multiple rows of child nodes of the MLD tree in parallel.

Abstract: A signal decoder, a method of detecting an RF signal at a MIMO receiver and a MIMO receiver are disclosed herein. In on embodiment, the signal decoder includes: (1) a tree pruner configured to reduce a number of nodes of an MLD tree to expand based on modulation properties of the transmitted radio signals and SE enumeration of at least a portion of the MLD tree and (2) a vector sorter configured to sort multiple rows of child nodes of the MLD tree in parallel.

Abstract: A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop instruction target address. The next PC value generator further includes a next PC value logic having a plurality of inputs: a first input coupled to an output of the discontinuity decoder, and a second input coupled to an output of the tight loop decoder. The next PC value logic provides as an output, without a stall, a control signal that a next PC value is to be loaded with the tight loop instruction target address if: the discontinuity decoder detects a discontinuity instruction, and the tight loop decoder detects a tight loop instruction.

Abstract: The present invention provides a dual mode mobile device that can use both cellular-based and IP-based applications with single application program interface and without having separate and distinct subsystems for each communications mode. The device may also include a power management module that considerably reduces the power consumption of the device by periodically entering a deep sleep mode for a predetermined sleep interval, changing power modes based on the status of one or more applications, automatically changing power modes based on incoming packets or a combination thereof. The device may also include a remote management module to diagnose, troubleshoot and solve problems involving one of the networks by using the device's ability to communicate using the other network. The dual mode capability of the mobile device allows a remote management server or operator to analyze, document and solve problems with the mobile device and/or its connections to a network.

Abstract: A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop instruction target address. The next PC value generator further includes a next PC value logic having a plurality of inputs: a first input coupled to an output of the discontinuity decoder, and a second input coupled to an output of the tight loop decoder. The next PC value logic provides as an output, without a stall, a control signal that a next PC value is to be loaded with the tight loop instruction target address if: the discontinuity decoder detects a discontinuity instruction, and the tight loop decoder detects a tight loop instruction.

Abstract: A distributed arithmetic multiply/accumulate (MAC) unit for computing inverse discrete cosine transformations (IDCTs). In one embodiment, the distributed arithmetic MAC unit includes: (1) a first pipeline stage configured to perform dot products on received sequential input data and (2) a second pipeline stage coupled to the first pipeline stage and configured to compute additions and subtractions of the dot products to yield sequential output data.

Abstract: A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes write enable logic and an execution unit. The write enable logic produces write enable signals dependent upon received attributes, and the execution unit saves results of instructions of conditional execution instruction groups dependent upon the write enable signals.

Abstract: A processor is disclosed including an instruction unit and an execution unit. The instruction unit fetches and decodes instructions, including a conditional execution instruction. The conditional execution instruction specifies one or more instructions to be conditionally executed (i.e., “target instructions”), a register of the processor, and a condition within the register. When the instruction unit fetches and decodes the conditional execution instruction, the execution unit saves results of the one or more target instructions dependent upon the existence of the specified condition in the specified register during execution of the conditional execution instruction. A system including the processor is described, as is a method for conditionally executing at least one instruction.

Abstract: A cell library which enables reduced quantization over-design in large scale circuit design is provided. Library cells having the same cell function have drive strengths selected to provide delays about equal to a predetermined set of design delays, at a nominal load corresponding to the cell function. In contrast, conventional cell libraries typically have drive strengths which correspond to a predetermined set of cell physical areas. Preferably, the spacing between adjacent design delays is a non-decreasing function of cell drive strength. Such spacing reduces quantization induced over-design compared to conventional cell libraries which have a design delay spacing that is a decreasing function of cell drive strength. On-chip clock distribution is an important application where cell libraries of the invention can provide significant advantages.

Abstract: The present invention provides for a security system for an electronic device that, in one embodiment, includes a processor with a software access key encrypted thereon and a software application with a processor access key encoded therein so that operation of the electronic device and execution of the software application requires both the software access key and the processor access key.

Abstract: A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple state machines simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes multiple attribute queues simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes write enable logic and an execution unit.

Abstract: An in-circuit emulation debugger and method of operating an in-circuit emulation debugger to test a digital signal processor (DSP). In one embodiment, the in-circuit emulation debugger includes: (1) a device emulation unit, coupled to a collocated DSP core, for emulating circuitry that is to interact with the DSP core, (2) an external processor interface, coupled to the device emulation unit, that receives control signals from an external processor that cause the device emulation unit to provide a test environment for the DSP core and (3) a breakpoint detection circuit, associated with the device emulation unit, that responds to preprogrammed breakpoints based on occurrences of events both internal and external to the DSP core.