Abstract: The present disclosure provides a tessellation data processing method, system, medium and vector graphics processing device. The method includes: constructing a data structure including a content table and information tables in memory; when a vector line generated by tessellation intersects an horizontal/vertical line to obtain a new intersection, reading an address and number of Xnodes or Ynodes of an information table in the content table corresponding to a row/column corresponding to the Y/X coordinate of the intersection; according to the address of the information table and the number of X/Ynodes of the information table, reading corresponding X/Ynodes from the memory; comparing information of the intersection with the X/Ynodes, and updating the X/Ynodes in the information table, or adding an X/Ynode to the information table at a position corresponding to the Y/X coordinates.

Abstract: The present disclosure provides a cooperative access method, system, and architecture of an external storage.

Abstract: The present disclosure provides a TWS earphone communication method and system, and TWS earphones. The method includes: when an audio source sends a data packet and a main earphone correctly receives the data packet, the main earphone sends acknowledgment information in an acknowledgment information slot; when the data packet is incorrectly received by the main earphone, no information is sent in the acknowledgment information slot; and when the data packet is received correctly by a secondary earphone, the secondary earphone does not send any information in the acknowledgment information slot. When the data packet is not received correctly by the secondary earphone, it sends interference information in the acknowledgment information slot.

Abstract: The present disclosure provides a method and system for synchronous audio playback of TWS earphones, The TWS earphones include a master earphone and a slave earphone; both the master earphone and the slave earphone include a first timer, a second timer, an audio DAC, and an audio playback phase-locked loop; the first timer and the second timer of the master earphone are respectively used to collect a real-time audio playback position of the master earphone and a public Bluetooth clock; the first timer and the second timer of the slave earphone are respectively used to collect a real-time audio playback position of the slave earphone and a local Bluetooth clock; the slave earphone calibrates audio data in the audio DAC, and the first timer and the audio playback phase-locked loop of the slave earphone, to achieve synchronization between the master earphone and the slave earphone.

Abstract: The present disclosure provides a TWS earphone interaction method and system, and TWS earphones. When a main earphone and a secondary earphone receive a data packet sent by an audio source, within a residual slot of a data transmission slot, the main earphone and the secondary earphone can perform data interaction, wherein the residual slot is the remaining data transmission slot after the data packet is transmitted. When a data packet is received, the main earphone sends acknowledgment information to the audio source, within a residual slot of a next data transmission slot, the main earphone and the secondary earphone can perform data interaction, wherein the residual slot is the remaining of the next data transmission slot after the acknowledgment information is sent.

Abstract: The present disclosure is directed to methods to generate a packed result array using parallel vector processing, of an input array and a comparison operation. In one aspect, an additive scan operation can be used to generate memory offsets for each successful comparison operation of the input array and to generate a count of the number of data elements satisfying the comparison operation. In another aspect, the input array can be segmented to allow more efficient processing using the vector registers. In another aspect, a vector processing system is disclosed that is operable to receive a data array, a comparison operation, and threshold criteria, and output a packed array, at a specified memory address, comprising of the data elements satisfying the comparison operation.

Abstract: The present disclosure provides an automatic mismatch calibration circuit and method, and a radio frequency receiver system. The automatic mismatch calibration circuit includes: at least one direct current (DC) offset estimation and calibration module coupled to a rear end of a radio frequency (RF) receiver to estimate a DC offset of received signals transmitted in an I channel and a Q channel to obtain an I-channel-DC-component and a Q-channel-DC-component, and compensate the I-channel-DC-component and the Q-channel-DC-component to the received signals corresponding to the I channel and the Q channel to achieve DC offset calibration. The present disclosure solves the problem that the existing mismatch calibration circuit cannot meet the low power consumption requirements of the system.

Abstract: The present disclosure provides a data reading/writing method and system for in 3D image processing, a storage medium and a terminal. The method includes the following steps: dividing a 3D image horizontally based on the vertical sliding technology, the 3D image is divided into at least two subimages, a processing data of each subimage is stored in a circular buffer, after the subimage is processed, an overlapping portion data required by next subimage is retained in the circular buffer; dividing a multi-layer network of an image processing algorithm into at least two segments, the data between adjacent layers in each segment only interact through buffer, not through DDR.

Abstract: The present disclosure provides a mixing circuit with high harmonic suppression ratio, including: a multi-phase generation module, which receives a first input signal and generates eight first square wave signals with a phase difference of 45°; a quadrature phase generation module, which receives a second input signal and generates four second square wave signals with a phase difference of 90°; a harmonic suppression module, connected with an output end of the quadrature phase generation module to filter out higher order harmonic components in the second square wave signals; and a mixing module, connected with output ends of the multi-phase generation module and the harmonic suppression module to mix output signals of the multi-phase generation module and the harmonic suppression module. The mixing circuit with high harmonic suppression ratio adds a harmonic suppression module on the basis of multi-phase mixing, thereby improving the harmonic suppression ratio of the output signal.

Abstract: The present disclosure provides an edge anti-aliasing graphic processing method, system, storage medium and apparatus. The method includes: obtaining four sampling points by double sampling a pixel horizontally and vertically and performing rasterization to the pixel, determining whether the four sampling points are covered by a triangle; performing a depth value test on the pixel, and determining whether the four sampling points of the pixel are all covered by the triangle; performing final color processing on the pixel, determining whether the four sampling points are covered by the triangle, if the four sampling points are all covered by the triangle, copying a color of the pixel center point to the four sampling points, if not all the four sampling points are covered by the triangle, mixing colors of the four sampling points of the pixel.

Abstract: The present disclosure provides a radio frequency (RF) front-end of a low power consumption and fully automatic adjustable broadband receiver, including a low-noise amplification module, amplifying an broadband single-ended RF signal, and converting it into differential current signal; a local oscillator, generating a local oscillator signal; an quadrature mixer, quadraturely mixing the differential current signal and the local oscillator signal to generate intermediate frequency differential current signals; a transimpedance amplifier, converting the intermediate frequency differential current signal into an intermediate frequency differential voltage signal; an IIP2 calibration module, reducing the IIP2 effect of the RF front end; a received signal strength indicator module, sending the first amplification factor control signal and the differential mismatch control signal to the low noise amplification module, and sending the second amplification factor control signal to the transimpedance amplifier, thereb

Abstract: The present disclosure provides an automatic mismatch calibration circuit and method, and a radio frequency receiver system. The automatic mismatch calibration circuit includes: at least one direct current (DC) offset estimation and calibration module coupled to a rear end of a radio frequency (RF) receiver to estimate a DC offset of received signals transmitted in an I channel and a Q channel to obtain an I-channel-DC-component and a Q-channel-DC-component, and compensate the I-channel-DC-component and the Q-channel-DC-component to the received signals corresponding to the I channel and the Q channel to achieve DC offset calibration. The present disclosure solves the problem that the existing mismatch calibration circuit cannot meet the low power consumption requirements of the system.

Abstract: The present disclosure provides a radio frequency (RF) front-end of a low power consumption and fully automatic adjustable broadband receiver, including a low-noise amplification module, amplifying an broadband single-ended RF signal, and converting it into differential current signal; a local oscillator, generating a local oscillator signal; an quadrature mixer, quadraturely mixing the differential current signal and the local oscillator signal to generate intermediate frequency differential current signals; a transimpedance amplifier, converting the intermediate frequency differential current signal into an intermediate frequency differential voltage signal; an IIP2 calibration module, reducing the IIP2 effect of the RF front end; a received signal strength indicator module, sending the first amplification factor control signal and the differential mismatch control signal to the low noise amplification module, and sending the second amplification factor control signal to the transimpedance amplifier, thereb

Abstract: The present disclosure is directed to a method of utilizing a lookup table (LUT) where the index to the LUT does not need to be modified or changed in cases where the LUT is larger than a single register or larger than a set of available registers. In another embodiment, a processor instruction is disclosed that can take in one or more indices to a LUT and return the lookup results, without modifying the indices, when the LUT is larger than the available register data element space. In another embodiment, a SIMD processor system is disclosed that can implement a processor instruction to utilize a LUT that is larger than the available register data element space without needing to modify the parameterized index when a different subset of the LUT is swapped into the available registers.

Abstract: The present disclosure provides an edge anti-aliasing graphic processing method, system, storage medium and apparatus. The method includes: obtaining four sampling points by double sampling a pixel horizontally and vertically and performing rasterization to the pixel, determining whether the four sampling points are covered by a triangle; performing a depth value test on the pixel, and determining whether the four sampling points of the pixel are all covered by the triangle; performing final color processing on the pixel, determining whether the four sampling points are covered by the triangle, if the four sampling points are all covered by the triangle, copying a color of the pixel center point to the four sampling points, if not all the four sampling points are covered by the triangle, mixing colors of the four sampling points of the pixel.

Abstract: A data collection system includes one or more input sensing devices and a data collection device. The data collection device includes data collection circuitry that is continuously activated to capture measurement data samples from the one or more input sensing devices and locally store the measurement data samples. The data collection device also includes a digital processor that is coupled to the data collection circuitry and is activated to locally perform a sample analysis of the measurement data samples, wherein the sample analysis is a regular analysis of routine measurement data samples when the measurement data samples are without a triggering event, and wherein the sample analysis is an event analysis when the measurement data samples include a triggering event. A data collection integrated circuit and a measurement data sample collection method are also included.