Abstract: Circuits and methods for protecting a circuit from an electrostatic discharge (ESD) event are disclosed herein. One such method includes detecting when a circuit to be protected is powering up and disabling an output driver of the circuit to be protected when the circuit is powering up. The power up sequence, for example, may be the result of a sensed ESD event. In addition, the present disclosure includes a circuit that comprises an ESD sensing circuit and a disable circuit. The ESD sensing circuit includes an RC circuit connected between VDD and VSS and a first inverter connected between a second inverter and a node that connects a resistor with a capacitor of the RC circuit. The disable circuit includes a first PMOS transistor and a first NMOS transistor, the first PMOS transistor configured to receive an EN signal from the second inverter, and the first NMOS transistor configured to receive an EN signal from the first inverter.

Abstract: A memory refresh method applicable in a system memory is disclosed. The memory system comprises a plurality of memory ranks. It is to determine whether an access request corresponds to the memory rank, and an idle auto-refresh number of the memory rank is calculated if there is no access request corresponds to the memory rank. The memory rank is switched from an auto-refresh mode to a self-refresh mode when the idle auto-refresh number of the memory rank reaches a predetermined value.

Abstract: The invention provides a method for implementing varying service quality grades in a network switch. First, a plurality of users of the network switch is classified into a plurality of service quality grades according to a contributing factor of the plurality of the users. Each of the plurality of users is then connected to the network switch via one of a plurality of ports of the network switch according to its service quality grade. An original priority of a packet in the network switch is then determined. An adjusted priority of the packet is then determined according to both the original priority of the packet and a priority adjustment table of an ingress port of the packet. Each of the plurality of ports has a corresponding priority adjustment table, and each of the priority adjustment tables includes a mapping relationship between the original priority and the adjusted priority.

Abstract: A graphics processing unit (“GPU”) is configured to interrupt processing of a first context and to initiate processing of a second context upon command so that multiple programs can be executed by the GPU. The CPU creates and the GPU stores a run list containing a plurality of contexts for execution, where each context has a ring buffer of commands and pointers for processing. The GPU initiates processing of a first context in the run list and retrieves memory access commands and pointers referencing data associated with the first context. The GPU's pipeline processes data associated with first context until empty or interrupted. If emptied, the GPU switches to a next context in the run list for processing data associated with that next context. When the last context in the run list is completed, the GPU may switch to another run list containing a new list of contexts for processing.

Abstract: A data buffer device that includes a write unit and a read unit, and is disposed between a first interface device and a second interface device is provided. The write unit further includes a first write buffer, a second write buffer and a write controller. The write controller controls the first write buffer and the second write buffer to receive and transmit data from the first interface device to the second interface device alternatively according to the requests of the first interface device and the second interface device. The read unit further includes a first read controller, a first read buffer and a second read buffer. The read controller controls the first read buffer and the second read buffer to receive and transmit data from the second interface device to the first interface device alternatively according to the requests of the first interface device and the second interface device.

Abstract: A multi-chip package structure is provided with a first chip, a substrate adjacent to the first chip, a plurality of contacts connecting the first chip and the substrate, a second chip disposed between the first chip and the substrate and connecting to the first chip, and a underfill film, wherein the underfill film covers the contact to isolate the contact from the second chip, wherein an empty space is defined by the second chip and the substrate so that the second chip does not contact the substrate.

Abstract: A method of managing power consumption of a network interface is provided. The method is capable of cutting off the power and the clock signal supply to the MAC and the PHY receiving terminals of the network interface when the user disables the wake-up function, and when the user enables the wake-up function, the power and the clock signal are supplied to the receiver of the medium access control unit and the receiver of the physical layer unit.

Abstract: A method for detecting the data strobe signal from a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The method executes a data reading process at first and records the latency period of the data read process to be a basis for detecting the arrival timing of the preamble in the data strobe signals in the subsequent data reading process.

Abstract: An integrated circuit design for differential variable capacitors uses an integration method to integrate an integrated circuit having differential variable capacitors as a whole, and takes the parasitic effect into consideration for the manufacturing process to lower the circuit inaccuracy and reduce the chip size effectively. Such arrangement lowers the manufacturing cost, identifies the quality of loading quality of the overall variable capacitance during the manufacture, and further controls the quality of loading capacity of the overall variable capacitance effectively. Furthermore, this invention does not need to reposition for the symmetrical position of the coils, and thus giving a very precise positioning to reduce the level of difficulty for the manufacture.

Abstract: A disc playing method and related system without interruption is disclosed. First, the data blocks on a disc (such as a DVD) is previewed without playing. Next, the error ratio of the data block is determined. If the error ratio of the data block exceeds a predetermined threshold, the address of the data block is recorded in an error data table. Finally, the data blocks not recorded in the error data table are played.

Abstract: A conversion mixer includes a mixing circuit, a duplicating circuit and a loading circuit. The mixing circuit receives a couple of first input signals and a couple of second input signals and mixes the couple of first input signals with the couple of second input signals to output a couple of mixed signals. The duplicating circuit coupled to the mixing circuit receives the couple of mixed signals and duplicates the couple of mixed signals to output a couple of duplicated signals. The loading circuit coupled to the duplicating circuit receives the couple of duplicated signals and outputs a couple of output signals according to the couple of duplicated signals.

Abstract: A power control method is provided for an optical disk drive. The optical disk drive has an optical read/write module for accessing an optical storage media. The power control method includes the following steps: measuring the temperature of the optical read/write module; predicting a threshold current of the optical read/write module according to the temperature; determine the accessing mode of the optical storage media; measuring the output power of the optical read/write module; computing a first current required for the optical read/write module according to the output power of the optical read/write module and a base power in the accessing mode; compensating the computed first current according to the predicted threshold current; and driving the optical read/write module according to the first current.

Abstract: A power management method. The power management method for a wireless network having a plurality of stations (STAs) comprises receiving a data frame, detecting a destination STA in accordance with the data frame, and entering a low power state if not the destination STA for a first power-save (PS) duration determined according to a network allocation vector (NAV) of each STA not the destination STA, updated with a duration information of the received data frame duration determined according to a network allocation vector (NAV) of the data frame.

Abstract: The present invention relates to a subtitle file loading method for loading subtitle files from a disc to a memory of a disc player. The memory has a first memory block and a second memory block. A first group of subtitle files is first loaded into the first memory block. Then, the first group of subtitle files in the first memory block is transferred to a subtitle file decoder for decoding, while a second group of subtitle files is loaded into the second memory block. Thereafter, the second group of subtitle files is transferred to the subtitle file decoder for decoding, and a third group of subtitle files is loaded into the first memory block. The steps described above are repeated in an alternative process until all subtitle files are loaded into the memory.

Abstract: A system and method for filtering spurious transitions from a digital signal is disclosed. The system includes a latch, a timer, and a logic circuit. Upon a transition of the digital signal, the latch holds the digital signal to block any additional transitions and the timer, which is connected to the output of the latch, begins a timing operation that creates a filter pulse. The output of the timer is then combined with the digital signal to filter the spurious transitions that may occur after the transition of the signal. The timer is implemented as an integrator that generates a ramp signal using a stable current source and a comparator that trips when the ramp signal passes a threshold. Use of the integrator and comparator saves space and reduces the system's operating current compared to the conventional approach.

Abstract: Graphics processing units (GPUs) are used, for example, to process data related to three-dimensional objects or scenes and to render the three-dimensional data onto a two-dimensional display screen. One embodiment, among others, of a GPU is disclosed herein, wherein the GPU includes a control device configured to receive vertex, geometry and pixel data. The GPU further includes a plurality of execution units connected in parallel, each execution unit configured to perform a plurality of graphics shading functions on the vertex, geometry and pixel data. The control device is further configured to allocate a portion of the vertex, geometry and pixel data to each execution unit in a manner to substantially balance the load among the execution units.

Abstract: A voltage level shifter converts an input signal into an output signal. While the input signal is high to the output signal is high either. Moreover, while the input signal is low the output signal is low either.

Abstract: A phase lock loop device further includes a probability shaping device provided between a phase detection device and charge pump and loop filter (CPLF) device. The probability shaping device operates to reduce the frequency of outputting up-index or down-index; thereby shaping probability distribution to reduce degradation due to mismatching of the CPLF device.

Abstract: In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the memory unit discharges the corresponding row line of the objective memory unit according to a discharging signal and a column selective signal. When the objective memory unit is enabled, the voltage level of the corresponding column line is changed, if the voltage level reaches a threshold voltage level, the auxiliary module enhances the increment of the voltage level of the column line.

Abstract: A power saving method and system thereof is disclosed. When the central processing unit is under a non-snooping sleep state and a peripheral device sends a bus master request, a chip will drive the central processing unit waking from the non-snooping sleep state and entering a system management mode for executing an interrupt service routine that makes the central processing unit in halt status. The central processing unit is then driven to enter a snooping sleep state for snooping the bus master request. After the execution of the bus master request, the chip will drive the central processing unit to leave the snooping sleep state and return to the non-snooping sleep state for power consumption conservation.