Abstract: Circuits for generating multiple clocks for computer systems are disclosed. One such system includes a circuit configured to generate a core clock, a system bus clock, and a peripheral clock. The frequency of one of the clocks can be reduced or altered without altering the frequencies at which the other clocks oscillate. Also disclosed are methods for incorporating or utilizing the disclosed circuits.

Abstract: A method of power management of a CPU connects to a plurality of host bridges. The method is applied to a CPU connecting to the host bridges. When the host bridges are detected as no bus master signal being received, a command is transmitted to force the host bridges not to transmit the bus master signal to the CPU when they receive the bus master signal. After the CPU enters the C3 state, if the host bridges are detected that any one of the host bridges receives the bus master signal, the CPU is forced to quit the C3 state, and the host bridges are forced to transmit the bus master signal to the CPU.

Abstract: In a data transmission coordinating method, the computer system enters a coordinating state, and a first signal is issued from the central processing unit to the data transmission standard storage unit of the bridge chip. In response to the first signal, a second signal is issued from the data transmission standard storage unit of the bridge chip to the central processing unit to inform the central processing unit of a first operable transmission standard of the bridge chip. After the computer system exits the coordinating state, data transmission between the central processing unit and the bridge chip is performed according to the first operable transmission standard in a first condition.

Abstract: An output circuit includes a detector receiving a parallel data signal, detecting a level change degree for the parallel data signal between a first time point and a second time point, and outputting a select signal according to the level change degree; a delay adjusting device receiving and differentially delaying the parallel data signal into a first and a second delayed parallel data signals with a first and a second delay time, respectively; and a first multiplexer electrically connected to the detector and the delay adjusting device, and selecting one of the first and the second delayed parallel data signals to be outputted in response to the select signal.

Abstract: An inductor comprises first and second winding portions symmetrically arranged in an insulating layer on a substrate. Each of the first and second winding portions comprises at least two semicircular conductive traces concentrically arranged. At least one of the relatively outer semicircular conductive traces has a cross section smaller than at least one of the relatively inner semicircular conductive traces.

Abstract: A power saving method applied to a central processing unit under a non-snooping sleeping state with a bus master request from a peripheral device is presented. In accordance with the present invention, first prohibit the central processing unit from fetching instruction. Then drive the central processing unit entering a snooping sleeping state and enabling the arbiter for transferring the bus master request to the central processing unit. After the central processing unit completes the bus master request, the arbiter is disabled and the central processing unit is driven to leave the snooping sleeping state and return back to the non-snooping sleeping state. Therefore, the power consumed by the central processing unit is reduced so as to save power.

Abstract: A RF variable gain amplifier with an extended linear tuning range is disclosed. The variable gain amplifier employs a wide swing cascode mirror formed by two cascode transistors and two gain transistors. The two cascode transistors track each others so are the two gain transistor. The gain transistors operate on the saturation region.

Abstract: In a state negotiation method of a PCI-E upstream device supporting multiple downstream configurations, a state of a second link asserted by a second state machine of the PCI-E upstream device is detected when a first link asserted by a first state machine of the PCI-E upstream device is ready to change from a first state to a second state in a specified duration. A negotiating procedure is performed to have the first link and the second link enter the second state simultaneously if the second link is detected to be in the first state within the specified duration.

Abstract: A hybrid IR transmission system implements at least two IR transmission protocols with a common IR transceiver. The hybrid IR transmission system includes an IR decoding circuit, a common IR transceiver and a filter circuit. The IR decoding circuit includes an IrDA module for decoding IR signals in IrDA protocol and a CIR module for decoding IR signals in CIR protocol. The common IR transceiver receives a first IR signal in either IrDA or CIR protocol. The filter circuit processes the first IR signal into a second IR signal accessible to one of the IrDA module and the CIR module for decoding.

Abstract: A method is used for changing colors of a first image frame to form a second image frame. Palette index values of the first image frame are first read. Then, color change index values specific to the second image frame and correlating to the palette index values are read respectively via a color change index array. Afterwards, color value sets corresponding to the color change index values are read respectively. Consequently, the second image frame is displayed with colors indicated by the color value sets.

Abstract: The present invention provides a method for receiving an instruction for varying the bus frequency from a current bus frequency to a new frequency. The method may include storing a group of parameters corresponding to a second frequency, disabling a link connected to the host bus at a first frequency while the host bus is being operated with parameters corresponding to the first frequency, updating the parameters for operating the host bus with the group of parameters, and enabling the link at the second bus frequency to operate the host bus with the group of parameters.

Abstract: A device for protecting a slicer in reading signals on a defect disc from disturbance and instability is provided. The device includes a defect detection unit, a slicer and a logic combination unit. The defect detection unit receives a plurality of defect detection signals to detect various defects for setting a plurality of defect flag signals, wherein the plurality of defect detection signals at least include an envelope signal of a RF signal and bit modulation signals. The slicer receives and digitalizes the RF signal. The logic combination unit performs logic operation on the defect flag signals in order to detect a specified defect and to trigger defect protection for the slicer. A method for protecting a slicer in reading signals on a defect disc is also provided.

Abstract: Various embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a software programmable core processing unit having a variable length decoding unit (VLD) unit configured to execute a shader, the shader configured to selectively implement decoding of a video stream coded based on a plurality of different coding methods to provide a decoded data output, wherein the decoding is implemented using a combination of software and hardware.

Abstract: Various embodiments of decoding systems and methods are disclosed. One method embodiment, among others, comprises providing a shader configurable with a plurality of instruction sets to decode a video stream coded a plurality of different coding methods, loading the shader having one of the plurality of instruction sets to a variable length decoding (VLD) unit of a software programmable core processing unit for execution thereof, and decoding the video stream by executing the shader on the VLD unit.

Abstract: A spiral inductor with a multi-trace structure having an insulating layer disposed on a substrate. A first spiral conductive trace with multiple turns is disposed on the insulating layer, wherein the outermost turn and the innermost turn of the first spiral conductive trace have a first end and a second end, respectively, and one of the first and second ends is connected to ground. A second spiral conductive trace with a single turn is disposed on the insulating layer and adjacent to the first spiral conductive trace, wherein the second spiral conductive trace is electrically connected to the turn that is connected to the ground and belongs to the first spiral conductive trace. The first spiral conductive trace has a relative outside and a relative inside, wherein the end of the first spiral conductive trace connected to ground and the second spiral conductive trace are located at different sides respectively.

Abstract: An apparatus providing for a secure execution environment, including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has secure execution mode logic that is configured to provide for a secure execution mode within the microprocessor for execution of the secure application program. The secure execution mode logic records the state of the microprocessor in a non-volatile indicator register upon entry into the secure execution mode and upon exit from the secure execution mode. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program. Transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.

Abstract: A hyper throughput packet transmission method for a wireless local area network operating in burst and protection mode is provided. A first CTS frame is sent, comprising an NAV to reserve the medium for a duration. Upon completion of the first CTS frame delivery, a plurality of data frames are delivered to the destination. Upon completion of the data frame delivery, a second CTS frame is sent to reserve the medium for another duration, such that the previous steps form a loop. Delivery of the data frames comprises, a data frame is delivered from the source to the destination, and after the data frame delivered, waiting for an ACK frame from the destination within one SIFS interval. Upon receipt of the ACK frame, if the following data frame is ready, the previous steps loop, otherwise the delivery is complete.

Abstract: A power state management method of north bridge. The north bridge monitors power transition state of processor; then adjusting operating clocks and operating voltage of the processor and the main memory according to the determined power state to saving power consumption.

Abstract: A manufacturing process of a chip package structure is provided. The manufacturing method uses fine pitch circuit processes, such as a TFT-LCD process or an IC process, to increase layout density and shorten electrical transmission pathways so that a higher electrical performance level is attained. First, a multi-layered interconnection structure with high-density bonding pads and fine pitch circuit is formed over a hard support base plate having a large area and high degree of planarity. A die is attached to a top surface of the multi-layered interconnection structure. A plurality of opening is formed on a bottom surface of the support base plate. Contacts are positioned into the openings in the support base plate such that the contacts are electrically connected to an inner circuit within the multi-layered interconnection structure.

Abstract: Various embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a software programmable core processing unit having a context-adaptive variable length coding (CAVLC) unit configured to execute a shader, the shader configured to implement CAVLC decoding of a video stream and provide a decoded data output.