Abstract: A programmable interconnect structure for an integrated circuit comprises: a pass-gate fabricated on a substrate layer to electrically connect a first node to a second node; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer; and a programmable method to select between isolating said first and second nodes and connecting said first and second nodes. A programmable buffer structure for an integrated circuit comprises: a first and a second terminal; and a programmable pull-up and a programmable pull-down circuit coupled between said first and second terminals; and a configuration circuit including at least one memory element coupled to said pull-up and pull-down circuits; and a programmable method to select between isolating said first terminal from second terminal by deactivating said pull-up and pull-down circuits, and coupling said first terminal to second terminal by activating said pull-up and pull-down circuits.

Abstract: A mask configurable semiconductor device, comprising: a first module layer having a plurality of circuit blocks including at least one programmable logic block; and a second module layer deposited substantially above the first module layer, including a read only memory (ROM) configuration circuit to program said logic block to a user specification.

Abstract: A programmable interconnect structure in an integrated circuit comprising: a plurality of wires; and a buffer comprising an input and an output, said buffer receiving a weak signal at the input and providing a buffered signal at the output; and a first programmable multiplexer comprising: a plurality of inputs and an output, wherein the inputs are coupled to said plurality of wires, and the output is coupled to said input of the buffer; and a user configurable configuration circuit comprising a plurality of memory elements, wherein the data stored in the memory elements select one of said plurality of wires to couple to said buffer input; and a second programmable multiplexer comprising: an input and a plurality of outputs, wherein the input is coupled to said output of the buffer and the outputs are coupled to said plurality of wires; and a user configurable configuration circuit comprising a plurality of memory elements, wherein the data stored in the memory elements select said buffer output to couple to o

Abstract: A highly economical alterable ASIC contains multiple fully optimized custom ASIC designs in one IC foot-print, each design utilizing the entire IC. The user can switch between multiple independently stored optimized logic applications instantly. The alterable ASIC comprises programmable logic blocks and user configurable circuits. Either random access memory (RAM) configuration circuits or mask configured read only memory (ROM) configuration circuits are stacked in separate module layers above a single logic module layer. Each RAM or ROM layer implements one design application and global control signals provide user selection. Alterable ASIC dissever the effective die cost, requires one smaller package, occupies one site on the PC board and needs less board level wires. An extremely low cost solution for system designs is realized with an alterable ASIC.

Abstract: A method of forming a semiconductor device includes fabricating digital circuits comprising a programmable logic circuit on a substrate; selectively fabricating either a memory circuit or a conductive pattern substantially above the digital circuits to program said programmable logic circuit; and fabricating a common interconnect and routing layer substantially above the digital circuits and memory circuits to connect digital circuits and one of the memory circuit or the conductive pattern.

Abstract: An inexpensive, re-configurable storage device for programmable and application specific logic is disclosed. A configurable storage device comprising a storage circuit including at least one output and at least one input capable of changing said output in a well defined response sequence; and a configuration circuit including at least one memory element to control a portion of said storage circuit; and a programmable means of altering said storage circuit response sequence. This allows the user greater flexibility in picking the most desired flip-flop from a variety of choices. The user programmed flip-flop option converts to an application specific conductive pattern with no change in storage device performance.

Abstract: A compact switching device for applications in integrated circuits is disclosed. The switching device comprises a P-type conductive channel and an N-type conductive channel, both formed on a very-thin semiconductor film. A lightly doped portion in each of said conductive channels is controlled by a single gate electrode formed on a dielectric layer above the channel regions. These lightly doped portions are designed to provide an enhanced conductive state by accumulating majority carriers at the surface, and a non-conductive state by fully depleting majority carriers from the entire thin-film thickness from the single gate electrode provided. Both gate electrodes are coupled to a common input, and both drain nodes are coupled to a common output. Design parameters are optimized to provide complementary devices side-by-side on a single geometry of the thin film, merged at the common drain node.

Abstract: A programmable wire structure for an integrated circuit, comprising: a programmable switch coupling two nodes, said switch having a first state that connects said two nodes, and said switch having a second state that disconnects said two nodes; and a configuration circuit coupled to said programmable switch, said circuit comprising a means to program said switch between said first and second state; and a first metal layer fabricated above a silicon substrate layer, said switch and said configuration circuit fabricated substantially above said first metal layer.

Abstract: A programmable look up table (LUT) circuit for an integrated circuit, comprising: one or more secondary inputs; and one or more configurable logic states; and two or more LUT values; and a programmable means to select a LUT value from a secondary input or a configurable logic state.

Abstract: A new Insulated-Gate Field-Effect Thin Film Transistor (Gated-FET) is disclosed. A semiconductor Gated-FET device comprises a lightly doped resistive channel region formed on a first semiconductor thin film layer; and an insulator layer deposited on said channel surface with a gate region formed on a gate material deposited on said insulator layer; said gate region receiving a gate voltage having a first level modulating said channel resistance to a substantially non-conductive state and a second level modulating said channel resistance to a substantially conductive state.

Abstract: A new Static Random Access Memory (SRAM) cell using a restoring device and a strong inverter is disclosed. An SRAM cell comprises a strong inverter and a strong access transistor constructed on a high-mobility semiconductor substrate layer. An N to 1 programmable multiplexer positioned above the inverter provides the input to said strong inverter from N available discrete voltage levels. A high mobility conducting path is used to read data quickly, while very small programmable elements vertically integrated in one or more planes increase the storage density at no extra area penalty. N data values are stored in one latch location, reducing memory area and cost significantly without sacrificing on time to access the stored data.

Abstract: A semiconductor device with two selectable manufacturing configurations, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, wherein in a first selectable configuration a plurality of memory circuits are formed to control a portion of the circuit blocks, and wherein in a second selectable configuration a conductive pattern is formed to control substantially the same portion of the circuit blocks.

Abstract: A new Static Random Access Memory (SRAM) cell using Thin Film Transistors (TFT) is disclosed. In a first embodiment, an SRAM cell comprises a strong inverter and a strong access device constructed on a semiconductor substrate layer, and a weak inverter and a weak access device constructed in a semiconductor thin film layer located vertically above the strong devices. The strong devices are used in the data read and write paths, and the weak devices are used for latch feed-back and sector data erase. This first embodiment is used for high density and high speed memory applications. In a second embodiment, an SRAM cell comprises thin film inverters and thin film access devices constructed in a semiconductor thin film layer located substantially above logic transistors. The TFT SRAM cell is buried above the logic gates of an Integrated Circuit to consume no extra Silicon real estate. This second embodiment is used for slow access and Look-Up-Tables type memory applications.

Abstract: A switching device for integrated circuit applications is disclosed. A first switching device includes a first device between a first voltage supply and a common output, a second device between a second voltage supply and common output, and a common input to control said first and second devices. Said first and second devices are constructed as complementary Gated-FET devices, wherein the conductive path of a Gated-FET comprises a resistive channel of the same dopant type as source and drain regions. A second switching device includes a first device between a first voltage supply and a common output, a second device between a second voltage supply and common output, and a common input to control said first and second devices. The conductive paths of said first and second devices are comprised of a single geometry of a semiconductor material.

Abstract: A new Static Random Access Memory (SRAM) cell using Thin Film Transistors (TFT) is disclosed. In a first embodiment, an SRAM cell comprises a strong inverter and a strong access device constructed on a semiconductor substrate layer, and a weak inverter and a weak access device constructed in a semiconductor thin film layer located vertically above the strong devices. The strong devices are used in the data read and write paths, and the weak devices are used for latch feed-back and sector data erase. This first embodiment is used for high density and high speed memory applications. In a second embodiment, an SRAM cell comprises thin film inverters and thin film access devices constructed in a semiconductor thin film layer located substantially above logic transistors. The TFT SRAM cell is buried above the logic gates of an Integrated Circuit to consume no extra Silicon real estate. This second embodiment is used for slow access and Look-Up-Tables type memory applications.

Abstract: A three-dimensional semiconductor device with two selectable manufacturing configurations includes a first module layer having a plurality of circuit blocks; and a second module layer formed substantially above the first module layer, wherein in a first selectable configuration a plurality of memory circuits are formed to store instructions to control a portion of the circuit blocks, and wherein in a second selectable configuration a predetermined conductive pattern is formed in lieu of the memory circuit to control substantially the same portion of the circuit blocks.