Abstract: Techniques for providing a coefficient scaling operational unit to perform the coefficient scaling computation for various image compression schemes are disclosed. To minimize multiple units, each for one image encoding/decoding scheme (e.g., MPEG4 and WMV9), a single coefficient scaling operational unit is designed to accommodate various standards. In one embodiment, the coefficient scaling operational unit comprises an arithmetic logic unit. The arithmetic logic unit operates in accordance with a formula involving multiplication and division. Parameters such as coefficients and quantization parameters are provided to perform the coefficient scaling operation.

Abstract: Efficient search window storage schemes for motion estimation in video signal processing are disclosed. According to one embodiment, motion estimation is carried out as follows: allocating a ring buffer to store at least critical number of macro-blocks of luminance data from a reference frame on the motion estimator, establishing a rule to relate each storage unit of the ring buffer with each of the macro-blocks of the reference frame, initializing the ring buffer by reading in one less than the critical number of macro-blocks from the reference frame, when the macro-block is located next to a border of the reference frame, generating one or more added border macro-blocks and storing into the corresponding position of the ring buffer in accordance with the rule, constructing the search window from the macro-blocks stored in the ring buffer, and conducting motion estimation of the current macro-block of the current frame with the search window.

Abstract: Techniques for compressing video stream in a video conference are disclosed. According to one aspect of the techniques, the method comprises obtaining a frame image sequence and selecting a reference frame image; determining whether an N-th frame image has acute movements relative to the reference frame image according to a predetermined threshold; and if yes, compressing and transmitting the N-th frame image; otherwise, not compressing and transmitting the N-th frame image; increasing N by 1 and repeating the above operations till the frame image sequence is over.

Abstract: Techniques to control computing systems without the physical touches by operators are disclosed. According to one aspect of the techniques, a non-touch operation system comprises a display unit for displaying operating objects, a capture unit for capturing images of an operator, an image processing unit, a line of sight analysis unit, a notification unit, an action analysis unit and an operation execution unit. The image processing unit is provided for calculating head's position parameters and eye's position parameters according to the captured images. The line of sight analysis unit is provided for determining a watching point of the operator on the display unit according to the calculated head's and eye's parameters and further determining one operating object according to the watching point. The notification unit is provided for informing the operator of the determined operating object in an apperceive way.

Abstract: Techniques for synchronizing clocks are disclosed. According to one aspect of the present invention, a pair of dividing coefficients a1 and a2 is obtained from a ratio of a theoretical frequency fs1 of the first source signal to a theoretical frequency fs_local of a desired local clock signal. A least common multiple expressed as T_c is obtained from the theoretical periods T1 and T2 of the first source signal and the second source signal. A relative error expressed as k is calculated from the first and second source clock signals in a period of T_c. The first source clock signal is then divided into a first local clock signal with a period equal to T1*a1 and a second local clock signal with a period equals to T1*a2 according to the dividing coefficients a1 and a2, respectively. The clock number m of the first local clock signal and the clock number n of the second local clock signal in the period of T_c are calculated according to the relative error k and the dividing coefficients a1 and a2.

Abstract: Techniques for distinguishing a pulldown field sequence from a normal field sequence are disclosed. According to one aspect of the techniques, the method for detecting pulldown field sequence comprises receiving a field sequence, combining two adjacent fields into one frame, detecting whether the combined frame has a combing phenomenon, if there is such a combing phenomenon, and determining a number of how many times the combing phenomenon occurs continuously in the combined frame. Based on the number, it can be determined whether the field sequence is a normal field sequence or a pulldown field sequence.

Abstract: Techniques pertaining to noise reduction are disclosed. According to one aspect of the present invention, noise in an audio signal is effectively reduced and a high quality of a target voice is recovered at the same time. In one embodiment, an array of microphones is used to sample the audio signal embedded with noise. The samples are processed according to a beamforming technique to get a signal with an enhanced target voice. A target voice is located in the audio signal sampled by the microphone array. A credibility of the target voice is determined when the target voice is located. The voice presence probability is weighted by the credibility. The signal with the enhanced target voice is enhanced according to the weighed voice presence probability.

Abstract: Techniques for enhancing bass effects in an audio signal are described. According to one embodiment, an audio input signal is filtered to produce a low frequency component thereof (a low frequency signal of the audio input signal). The low frequency signal expressed in time domain is transformed to a corresponding spectrum expression in frequency domain. A fundamental frequency signal of the low frequency signal in the frequency domain is determined to generate a plurality of harmonics that are then transformed back to the time domain. Both the audio input signal (delayed) and the harmonics are synthesized to produce an audio output signal whose bass is greatly enhanced.

Abstract: A circuit for controlling LEDs is described. The circuit includes a negative feedback closed-loop circuit provided to sense only the voltage on an LED. Any change in the voltage is caused to be corrected by the negative feedback closed-loop circuit in conjunction with a current source.

Abstract: Techniques pertaining to designs of a compensation voltage controlled current source (VCCS) used in low dropout voltage regulators are disclosed. According to one aspect of the present invention, a compensation voltage controlled current source (VCCS) is so designed to meet the low input/output voltage requirements. Various features of the VCCS are demonstrated through several embodiments.

Abstract: Techniques pertaining to device and method for controlling an analog signal are disclosed. Using a single connection (e.g., a connector or a pin) without an external resistive element (e.g., a resistor), an analog output is digitally controlled and produced. In one embodiment, a precisely controlled current is generated from coded data. A control unit is designed to control a working mode based on an input signal from the connection. The working mode includes a default mode, a programmable mode, a testing mode and a shutdown mode. Under the programmable mode, a user determines a signal coupled in from the connection as desired, and a code unit codes the signal in accordance with a predefined protocol. The code unit then sends the coded data to a decode unit. The decode unit is designed to generate or control the current by the decoded data.

Abstract: Techniques pertaining to driving LEDs on multiple branches of a circuit are disclosed. According to one aspect of the present invention, an LED drive circuit includes a boost circuit configured for receiving an input voltage and providing an output voltage according to a control signal, a selector configured for alternatively selecting one of the feedback signals as an output feedback signal and switching on a corresponding branch circuit, and a pulse-width modulation (PWM) controller configured for generating a pulse-width modulation signal as the control signal for the boost circuit according to the output feedback signal of the selector, essentially to match respective currents in the multiple branches.

Abstract: A direct memory access controller (DMAC) is disclosed. In one case, the DMAC is configured to manage a DMA transmission of mass data with non-continuous addresses with a nonvolatile memory. The DMAC has to transmit them in batches according to their respective continuous addresses but, different from the prior art systems, does not interrupt a CPU for each batch of the DMA transmissions. In a DMA transmission between a functional device and the nonvolatile memory, a central processor configures a link-list of cluster addresses, which is obtained from a FAT (i.e., a file allocated table) in the nonvolatile memory and may be non-continuous, in a logic address buffer. Then, a divide unit provided in the DMAC divides a non-continuous link-list of cluster addresses from the logic address buffer into a plurality of continuous sub-link-list of cluster addresses, thus the DMAC can configure each batch of DMA transmission according to the continuous sub-link-list of cluster addresses without causing impact on the CPU.

Abstract: Architectures for graphic engine chips with minimum impact on other resources are disclosed. According to one embodiment, a graphic engine architecture includes a scheduler that is configured to schedule an execution time for each of the drawing instructions sent in groups from a processor. Each drawing instruction includes a piece of time information. The scheduler is provided to fetch the drawing instructions from a FIFO buffer that buffers the drawing instructions. Subsequently, the drawing instructions are successively executed according to their scheduling.

Abstract: Techniques pertaining to a comparator circuit with reduced power consumption are disclosed. According to one aspect of the present invention, the comparator unit has a pair of input signal pins VIP and VIN, a pair of output signal pins VOR and VOS, and a clock signal pin CLK. In operation, when the CLK signal is at an idle voltage level, the comparator unit comes into an idle state. At the idle state, the comparator unit does not compare the two input signals VIP and VIN so that the output signals are identical. When the CLK signal is at a busy voltage level, the comparator comes into a busy state. At the busy state, the comparator compares the input signals VIP and VIN, and determines the values of the output signals VOR and VOS depending on the comparing result, e.g., if the input signal VIP is larger than the input signal VIN, the output signal VOR is high and the output signal VOS is low; otherwise, the output signal VOR is low and the output signal VOS is high.

Abstract: Techniques for simultaneously and efficiently eliminating echo and noise mixed in voice are disclosed. According to one aspect of the present invention, an adaptive filter system for eliminating noises and echo mixed in voice signal comprises a first signal adaptive filter, a first subtractor, a second adaptive filter and a second subtractor. The first signal adaptive filter estimates the noise mixed in the voice signal according to a reference noise. The first subtractor subtracts the noise estimated by the first adaptive filter from the voice signal to obtain a voice signal without the mixed noise. The second adaptive filter estimates the echo mixed in the voice signal according to a remote voice signal. The second subtractor subtracts the echo estimated by the second adaptive filter from the voice signal without mixed noise to obtain a clean voice signal.

Abstract: A scan mode is used in a voltage detection circuit. An oscillator in the circuit is always on and a system including the voltage detection circuit detects various abnormal conditions, such as overcharging, overdischarging and overcurrent one by one for some clocks. To reduce the power consumption, the voltage detection circuit is turned on only once for several clocks. The on-time is very short and lasts about only one tenth of a clock cycle time. In other times, the voltage detection circuit is turned off to save power consumption.

Abstract: A multifunctional driver controller capable to drive one or more voltage-controlled devices or current-controlled devices is described. The multifunctional driver controller comprises a selection unit receiving a control signal, one of a first reference voltage and a second reference voltage, the selection unit selecting either one of the first reference voltage and the second reference voltage per the control signal, and a control circuit receiving a reference voltage from the selection unit and a feedback signal from a load being driven by a controlled analog signal from the control circuits. The controlled analog signal is either a controlled voltage signal or a controlled current signal, the control circuit compares the reference voltage with the feedback signal and adjusts the controlled analog signal in reference to a difference between the reference voltage and the feedback signal until the feedback signal converges to the reference voltage.

Abstract: Techniques for storing and reading data on/from a hard disk are disclosed. According to one aspect of the present invention, a hard disk is provided with a parameter storage block for storing a number of parameters. One of the parameters is a last physical address the hard disk was accessed. The last physical address is used as a reference to read data segments onto the hard disk. Each of the data segments is a compressed version of a portion of data to be stored in the hard disk. A portion of the data is allocated in accordance with a predefined time period. Accordingly, the compressed data portion also includes a header including information about the compressed data portion. The information includes at least a compression scheme used as well as the time about the data portion. Based on how the data is stored, a corresponding reading method is also provided.

Abstract: Techniques for interchanging positions of external terminals of an integrated circuit chip are disclosed. According to one aspect of the present invention, a chip comprises at least a pair of external terminals for communicating with other components or circuits, an internal circuit and an interchangeable unit coupled between the external terminals and the internal circuit. The interchangeable unit is configured to interchange the external terminals electronically such that the chip remains compatible in various versions involving an change of the terminals thereof, wherein the an interchangeable unit is controllable externally by a selecting pin applicable to either a high level or a low level to cause the external terminals interchanged.