Abstract: A scan mode is used in a voltage detection circuit. An oscillator in the circuit is always on and a system including the voltage detection circuit detects various abnormal conditions, such as overcharging, overdischarging and overcurrent one by one for some clocks. To reduce the power consumption, the voltage detection circuit is turned on only once for several clocks. The on-time is very short and lasts about only one tenth of a clock cycle time. In other times, the voltage detection circuit is turned off to save power consumption.

Abstract: A multifunctional driver controller capable to drive one or more voltage-controlled devices or current-controlled devices is described. The multifunctional driver controller comprises a selection unit receiving a control signal, one of a first reference voltage and a second reference voltage, the selection unit selecting either one of the first reference voltage and the second reference voltage per the control signal, and a control circuit receiving a reference voltage from the selection unit and a feedback signal from a load being driven by a controlled analog signal from the control circuits. The controlled analog signal is either a controlled voltage signal or a controlled current signal, the control circuit compares the reference voltage with the feedback signal and adjusts the controlled analog signal in reference to a difference between the reference voltage and the feedback signal until the feedback signal converges to the reference voltage.

Abstract: Techniques for storing and reading data on/from a hard disk are disclosed. According to one aspect of the present invention, a hard disk is provided with a parameter storage block for storing a number of parameters. One of the parameters is a last physical address the hard disk was accessed. The last physical address is used as a reference to read data segments onto the hard disk. Each of the data segments is a compressed version of a portion of data to be stored in the hard disk. A portion of the data is allocated in accordance with a predefined time period. Accordingly, the compressed data portion also includes a header including information about the compressed data portion. The information includes at least a compression scheme used as well as the time about the data portion. Based on how the data is stored, a corresponding reading method is also provided.

Abstract: Techniques for interchanging positions of external terminals of an integrated circuit chip are disclosed. According to one aspect of the present invention, a chip comprises at least a pair of external terminals for communicating with other components or circuits, an internal circuit and an interchangeable unit coupled between the external terminals and the internal circuit. The interchangeable unit is configured to interchange the external terminals electronically such that the chip remains compatible in various versions involving an change of the terminals thereof, wherein the an interchangeable unit is controllable externally by a selecting pin applicable to either a high level or a low level to cause the external terminals interchanged.

Abstract: Techniques pertaining to a circuit architecture capable of controlling a current source to a predefined precision are disclosed. According to one aspect of the present invention, an automatic trimming circuit is proposed to automatically trim a current generated from a current generator or circuit in accordance with a reference current. The automatic trimming circuit includes a comparator, an ADC and a register. The comparator that may be implemented as a subtractor finds a difference between a generated current and a reference current. The difference is then digitized to an n-bit precision. A digital representation of the difference is then kept in a register and used subsequently correct or modify the generated current to produce a precisely controlled current.

Abstract: Various techniques for synchronizing illumination with an audio signal are disclosed. According to one aspect of the techniques, an audio signal continuously is received and processed one phase or period at a time in an analyzing or detecting unit. From one phase of the audio signal, a set of light controlling parameters are determined from a look-up-table. These light controlling parameters are used to adjust duty cycles of square waves used to drive a plurality of light sources such that the illumination produced is in accordance with the audio signal.

Abstract: Techniques for a simple file system for facilitating file transmission are disclosed. According to one aspect of the techniques, a storage device comprises a memory, a creation module, a status record module and a data reading/writing module. The creation module creates a parameter block, a file allocated table, a root directory and a data area in the memory. The starting address of the data area is calculated according to parameters in the parameter block. The status record module stores a last writing address of a last writing access to the memory. The data reading/writing module reads data from the data area according to the starting address and the last writing address.

Abstract: Techniques for multiple master devices accessing one or more slave devices via a single data bus are disclosed. According to one aspect of the techniques, a bus controller coupled between the master devices and the slave device, wherein the bus controller is configured to receive bus signals from the master devices, select one of the bus signals from one of the master devices and forwards the selected bus signal to the slave device. After the slave device receives the bus signal from the one of the master devices, the slave device sends a bus response signal to the master devices over the bus controller, and the master device from which the bus signal is selected identifies and receives the bus response signal.

Abstract: Techniques for managing access to a file allocation table in an external storage device are disclosed. According to one aspect of the techniques, an accelerated apparatus, as an interface, is provided between an external storage and a device (or a host processor thereof). The accelerated apparatus comprises a center controlling unit, a FAT storage sector calculating unit, a FAT storage sector accessing unit, a buffer and a result storing unit and configured to manage the access to the FAT so that the host process is freed up to perform other tasks.

Abstract: Techniques for transmitting data between devices based on two-dimensional symbols are disclosed, where the devices are generally not equipped with the traditional networking capabilities, or at least these traditional networking capabilities are not used for the data communication. According to one aspect of the techniques, two devices communicate with each other by displaying one or more two-dimensional symbols. Data is encoded into one or more symbols that are displayed on one of the devices. Images of the symbols are taken by another one of the devices to receive the data. These images are sequentially processed and decoded so that the data is now received. To accommodate various environments, the system is configured to adjust parameters pertaining to the symbols to achieve an optimum transmission rate.

Abstract: Techniques for extending memory addressing with more accessing range are disclosed. According to one aspect of the techniques, an apparatus for extending addressing space comprises a plurality of extended memories, each being allocated an unique identifier, a direct addressing memory reserving a data cell as a public identifier cell for receiving the identifier of each of the extended memories to be accessed, a decision unit determining that which one of the extended memories is to be accessed by comparing an identifier received by the public identifier cell with the identifier of each of the extended memories, and a mapping unit mapping one of the extended memories determined by the decision unit to be accessed onto the direct addressing memory so that the one of the extended memories can be indirectly accessed by directly accessing the direct addressing memory.