Abstract: A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.

Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.

Abstract: An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.

Abstract: A system and method is described for operating a computer memory system having a plurality of controllers capable of accessing a common set of memory modules. Access to the physical storage of the memory modules may be managed by configuration logical units (LUNs) addressable by the users. The amount of memory associated with each LUN may be managed in units of memory (LMA) from a same free LMA table maintained in each controller of the plurality of controllers. A request for maintenance of a LUN may be received from any user through any controller and results in the association of a free memory area with the LUN, and the remaining controllers perform the same operation. A test for misallocation of a free memory area is performed and when such misallocation occurs, the situation is corrected in accordance with a policy.

Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

Abstract: A hardware search structure determines the status of cache lines associated with a large disk array and at the same time reduces the amount of memory space needed for tracking the status. The search structure is configurable in hardware to different cache line sizes and different primary and secondary index sizes. A maintenance feature invalidates state record entries based both on their time stamps and on associated usage statistics.

Abstract: A storage processor identifies latency of memory drives for different numbers of concurrent storage operations. The identified latency is used to identify debt limits for the number of concurrent storage operations issued to the memory drives. The storage processor may issue additional storage operations to the memory devices when the number of storage operations is within the debt limit. Storage operations may be deferred when the number of storage operations is outside the debt limit.

Abstract: Cache lines are identified that provide incorrect data for read requests. The cache lines are invalidated before the incorrect data causes processing failure conditions. The cache lines providing incorrect data may be detected according to a number of the same read requests to the same cache lines. The cache lines may also be identified according to an amount of time between the same read requests to the same cache lines. The same read requests to the same cache lines may be identified according to associated start addresses and address lengths.

Abstract: A storage system creates an abstraction of flash Solid State Device (SSD) media allowing random write operations of arbitrary size by a user while performing large sequential write operations of a uniform size to an SSD array. This reduces the number of random write operations performed in the SSD array and as a result increases performance of the SSD array. A control element determines when blocks from different buffers should be combined together or discarded based on fragmentation and read activity. This optimization scheme increases memory capacity and improves memory utilization and performance.

Abstract: A circuit card for a data processing system includes a printed circuit board (PCB) and a carrier. The PCB includes opposing sides parallel to a mounting direction when the PCB is installed to a cage. The carrier is attached to the PCB and includes at least one guiding member offset from a normal direction of the PCB and guiding installation of the PCB in the cage. The cage includes a plurality of support plates extending along a first direction and aligned along a second direction perpendicular to the first direction of the cage to define a plurality of air flow channels. When the circuit card is mounted to one of the support plates by engaging the guiding member to the support plate, the PCB is offset from the support plate and located right in the air flow channel without being obstructed by the support plate.

Abstract: A cluster of storage control members connect different clients to different storage disks. Connection path information between the different clients and disks is discovered and distributed to the storage cluster members. The connection path information is then used to maintain coherency between tiering media contained in the different storage cluster members. Unique Small Computer System Interface (SCSI) identifiers may be associated with the different connection paths to uniquely identify particular storage disks connected to the clients.

Abstract: A fiber channel network is configured into different zones. A first zone of the fiber channel network is configured with an initiator port, a first virtual port for a first physical port on a storage proxy, and a first virtual port for a second physical port on the storage proxy. A second zone of the fiber channel network is configured with a storage target port, a second virtual port for the first physical port on a storage proxy, and a second virtual port for the second physical port on the storage proxy. The virtual ports configured on the storage proxy increase the amount of bandwidth in the fiber channel available for asymmetric data transfers.

Abstract: A storage proxy receives different abstracted memory access requests that are abstracted from the original memory access requests from different sources. The storage proxy reconstructs the characteristics of the original memory access requests from the abstracted memory access requests and makes prefetch decisions based on the reconstructed characteristics. An inflight table is configured to identify contiguous address ranges formed by an accumulation of sub-address ranges used by different abstracted memory access requests. An operation table is configured to identify the number of times the contiguous address ranges are formed by the memory access operations. A processor is then configured to prefetch the contiguous address ranges for certain corresponding read requests.

Abstract: Storage of digital data in non-volatile media such as NAND FLASH needs to take account of the errors in data retrieved from the memory. The error rate tends to increase with the number of write/erase cycles of a cell of memory and with the time that the data has been stored. To achieve a very low uncorrected bit error rate (UBER) a substantial amount of redundancy data needs to be stored for error correction purposes. A method and apparatus is disclosed where a first redundancy data is represented by a second redundancy data computed from the first redundancy data. The first redundancy data may not be stored and is reconstructed from the stored data using a same generation procedure as previously used. The reconstructed estimate of the first redundancy data is corrected by the second redundancy data, and is used to correct the underlying data.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: A storage processor is configured to identify a first disk drive and a second shadow drive associated with the first disk drive to an initiator. The storage processor receives storage commands from an initiator. When the storage commands access the first disk drive, the storage processor issues a first storage operation to the first disk drive. When the storage commands access the second shadow drive, the storage processor issues different storage operations to the first disk drive that are not supported by the initiator.

Abstract: A proxy manages write operations between devices that initiate write operations and one or more storage devices that store data for the write operations. A write log buffers the data for the write operations while the proxy waits for acknowledgments back from the storage device. The proxy is configured to copy at least some of the data from the write log into an overflow log when the data from the write operations is about to overflow the write log. The proxy device is further configured to maintain data consistency by delaying or blocking read operations until associated data from previously received write operations is acknowledged by the storage device.

Abstract: A storage access system stores block data into physical address blocks in a storage media. A last one of the physical address blocks that is either unfilled or only partially filled with the block data is used for storing extra data associated with the data blocks. A first portion of the last one of the physical storage blocks may be reserved for overflow data for different sizes of the block data. A second portion of the last one of the physical storage blocks may be used to store the validation information for the block data.

Abstract: A hardware search structure quickly determines the status of cache lines associated with a large disk array and at the same time reduces the amount of memory space needed for tracking the status. The search structure is configurable in hardware to different cache line sizes and different primary and secondary index sizes. A maintenance feature invalidates state record entries based both on their time stamps and on associated usage statistics.