Patents Assigned to Violin Memory, Inc.
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Patent number: 8635416Abstract: A storage processor is configured to identify a first disk drive and a second shadow drive associated with the first disk drive to an initiator. The storage processor receives storage commands from an initiator. When the storage commands access the first disk drive, the storage processor issues a first storage operation to the first disk drive. When the storage commands access the second shadow drive, the storage processor issues different storage operations to the first disk drive that are not supported by the initiator.Type: GrantFiled: March 2, 2011Date of Patent: January 21, 2014Assignee: Violin Memory Inc.Inventor: Erik de la Iglesia
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Patent number: 8634419Abstract: A reliable and scalable system and method of broadcasting information to other computer nodes in a communication network requires only O(2) time steps. According to one aspect, after broadcasting data in O(1) steps to all nodes in the network, the system and method provides a distributed reliability protocol to ensure data delivery which only requires an additional O(1) steps. Therefore, unlike in prior art approaches where the root or co-root is responsible for the reliable data delivery, each node in the network takes on responsibility to deliver the message to a partner/neighborhood node. The broadcasting method and system of the can be used as building block for most collective/distributive operations, and provides a significant performance advantage in parallel computer systems that have multicast/broadcast capabilities.Type: GrantFiled: December 1, 2010Date of Patent: January 21, 2014Assignee: Violin Memory Inc.Inventor: Matthias Oberdorfer
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Patent number: 8452929Abstract: A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.Type: GrantFiled: November 18, 2008Date of Patent: May 28, 2013Assignee: Violin Memory Inc.Inventor: Jon C. R. Bennett
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Patent number: 8443150Abstract: A storage proxy includes a cache resource. A processor is configured to receive read and write requests sent from an initiator to a target over a first proxy path. The processor invalidates the cache lines when the read and write requests are redirected over a second direct path between the initiator and the target or when some other event indicates the data in the cache lines may no longer be consistent with corresponding data in the target. The processor identifies addresses for at least some of the cache lines that were previously valid and reloads the data for the identified addresses from the target back into some the cache lines when the read and write requests are redirected back over the first proxy path or when consistency can resumed between the data in the cache lines and corresponding data in the target.Type: GrantFiled: September 24, 2010Date of Patent: May 14, 2013Assignee: Violin Memory Inc.Inventor: Erik de la Iglesia
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Patent number: 8417871Abstract: A storage access system provides consistent memory access times for storage media with inconsistent access latency and reduces bottlenecks caused by the variable time delays during memory write operations. Data is written iteratively into multiple different media devices to prevent write operations from blocking all other memory access operations. The multiple copies of the same data then allow subsequent read operations to avoid the media devices currently servicing the write operations. Write operations can be aggregated together to improve the overall write performance to a storage media. A performance index determines how many media devices store the same data. The number of possible concurrent reads varies according to the number of media devices storing the data. Therefore, the performance index provides different selectable Quality of Service (QoS) for data in the storage media.Type: GrantFiled: April 13, 2010Date of Patent: April 9, 2013Assignee: Violin Memory Inc.Inventor: Erik de la Iglesia
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Patent number: 8417895Abstract: A proxy device monitors memory access operations between clients and a storage media. The proxy device stores at least some of the data from the storage media in a faster tiering media and provides the data from the faster tiering media to the clients for certain associated memory access operations. The proxy is also configured to monitor Small Computer System Interface (SCSI) communications between the clients and the storage media and invalidate at least some data in the tiering media when particular SCSI messages in the SCSI communications indicate the tiering media contains data that is out of sync with the data in the storage media.Type: GrantFiled: June 4, 2010Date of Patent: April 9, 2013Assignee: Violin Memory Inc.Inventor: Erik de la Iglesia
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Patent number: 8402198Abstract: A hardware search structure quickly determines the status of cache lines associated with a large disk array and at the same time reduces the amount of memory space needed for tracking the status. The search structure is configurable in hardware to different cache line sizes and different primary and secondary index sizes. A maintenance feature invalidates state record entries based both on their time stamps and on associated usage statistics.Type: GrantFiled: May 28, 2010Date of Patent: March 19, 2013Assignee: Violin Memory, Inc.Inventors: Erik de la Iglesia, Som Sikdar, David Parker, Dommeti Sivaram
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Patent number: 8402246Abstract: A storage proxy monitors storage access operations. Different address alignments are identified between the storage access operations and data blocks in a storage media. A dominant one of the address alignments is identified. Data blocks are mapped into the storage media to remove the dominant address alignment. An array of counters can be used to track the address alignments for different storage access sizes and the address alignment associated with the highest number of storage access operations is used as the dominant address alignment.Type: GrantFiled: August 26, 2010Date of Patent: March 19, 2013Assignee: Violin Memory, Inc.Inventor: Erik de la Iglesia
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Patent number: 8397016Abstract: A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system.Type: GrantFiled: December 31, 2009Date of Patent: March 12, 2013Assignee: Violin Memory, Inc.Inventors: Nisha Talagala, Berry Kercheval, Martin Patterson, Edward Pernicka, James Bowen
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Publication number: 20130019057Abstract: A data storage array is described, having a plurality of solid state disks configured as a RAID group. User data is mapped and managed on a page size scale by the controller, and the data is mapped on a block size scale by the solid state disk. The writing of data to the solid state disks of the RAID group is such that reading of data sufficient to reconstruct a RAID stripe is not inhibited by the erase operation of a disk to which data is being written.Type: ApplicationFiled: July 11, 2012Publication date: January 17, 2013Applicant: Violin Memory, Inc.Inventor: Donpaul C. Stephens
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Publication number: 20130019062Abstract: A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module.Type: ApplicationFiled: July 11, 2012Publication date: January 17, 2013Applicant: Violin Memory Inc.Inventors: Jon C.R. Bennett, David M. Smith, Daniel C. Biederman
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Publication number: 20120221922Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.Type: ApplicationFiled: April 9, 2012Publication date: August 30, 2012Applicant: Violin Memory, Inc.Inventor: Jon C. R. Bennett
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Patent number: 8200887Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.Type: GrantFiled: March 26, 2008Date of Patent: June 12, 2012Assignee: Violin Memory, Inc.Inventor: Jon C. R. Bennett
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Patent number: 8112655Abstract: A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.Type: GrantFiled: October 3, 2008Date of Patent: February 7, 2012Assignee: Violin Memory, Inc.Inventors: Kevin D. Drucker, James H. Jones, Jon C. R. Bennett
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Patent number: 8090973Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.Type: GrantFiled: November 15, 2010Date of Patent: January 3, 2012Assignee: Violin Memory, Inc.Inventor: Jon C. R. Bennett
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Patent number: 8028186Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.Type: GrantFiled: October 17, 2007Date of Patent: September 27, 2011Assignee: Violin Memory, Inc.Inventor: Jon C. R. Bennett
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Patent number: 7907069Abstract: A method and system allows for fast compression and decompressing of data using existing repetitive interleaved patterns within scientific data (floating point, integer, and image). An advantage of the method and system is that it is so fast that it can be used to save time due to a lower amount of data transferred/stored in scenarios like network transfer, disk or memory storage, cache storage or any other real-time applications where time plays a crucial role.Type: GrantFiled: June 16, 2009Date of Patent: March 15, 2011Assignee: Violin Memory, Inc.Inventor: Matthias Oberdorfer
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Patent number: 7877490Abstract: A method for efficient communications with a cluster-based architecture preserves various aspects of integrity throughout one or more connections with a client, even in the midst of connection migration between nodes in the cluster. According to one aspect, the invention provides a mechanism for preventing the loss of packets arising from a TCP connection migration within the cluster. According to another aspect, the invention provides a mechanism for uniquely identifying conflicting TCP connections migrated to a common node. According to a still further aspect, the invention provides a distributed TCP timestamp mechanism so that the sender and receiver will have a consistent view of the timestamp even when each node has different local clock values and regardless of how many times the socket has been migrated.Type: GrantFiled: December 28, 2007Date of Patent: January 25, 2011Assignee: Violin Memory, Inc.Inventors: Nisha Talagala, Qing Huang, Rama Chitta, Martin Patterson