Abstract: A storage processor is configured to identify a first disk drive and a second shadow drive associated with the first disk drive to an initiator. The storage processor receives storage commands from an initiator. When the storage commands access the first disk drive, the storage processor issues a first storage operation to the first disk drive. When the storage commands access the second shadow drive, the storage processor issues different storage operations to the first disk drive that are not supported by the initiator.

Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

Abstract: Storage of digital data in non-volatile media such as NAND FLASH needs to take account of the errors in data retrieved from the memory. The error rate tends to increase with the number of write/erase cycles of a cell of memory and with the time that the data has been stored. To achieve a very low uncorrected bit error rate (UBER) a substantial amount of redundancy data needs to be stored for error correction purposes. A method and apparatus is disclosed where a first redundancy data is represented by a second redundancy data computed from the first redundancy data. The first redundancy data may not be stored and is reconstructed from the stored data using a same generation procedure as previously used. The reconstructed estimate of the first redundancy data is corrected by the second redundancy data, and is used to correct the underlying data.

Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

Abstract: A hardware search structure determines the status of cache lines associated with a large disk array and at the same time reduces the amount of memory space needed for tracking the status. The search structure is configurable in hardware to different cache line sizes and different primary and secondary index sizes. A maintenance feature invalidates state record entries based both on their time stamps and on associated usage statistics.

Abstract: The storage system uses a combination of checkpoint data and journal data to reconstruct an indirection table. The checkpoint data comprises compacted media addresses from the indirection table that are then stored in a relatively few number of media blocks. This allows the media controller to quickly read the compacted checkpoint data from the solid state media. The media controller generates the journal data from logical addresses and associated media addresses for additional write operations received while creating the checkpoint data. The media controller uses metadata when errors are identified in the checkpoint data or journal data.

Abstract: A memory system contains solid state media for storing data and uses volatile memory for storing an indirection table. The indirection table maps client addresses to media addresses in the solid state media. The solid state media also stores metadata summaries maintaining the mappings of the client addresses to the media addresses within the solid state media. A media controller is configured to reconstruct the indirection table in the volatile memory from the metadata summaries stored in the solid state media based on block timestamps identifying when the metadata summaries were stored in the solid state media.

Abstract: Cluster data is generated based on a history of storage operations. The cluster data may include an address range and an access history. The access history may comprise a bit pattern that represents a history of storage operations associated with a cluster. A prefix or counter may identify the number of storage operations identified in the bit pattern. The bit pattern and/or address range may be updated to reflect new storage operations associated with the cluster. The bit pattern then may determine when to cache data in a cache memory. The bit pattern tracks a large number of storage operations in a relatively small amount of memory enabling quick effective caching decisions.

Abstract: A storage processor identifies latency of memory drives for different numbers of concurrent storage operations. The identified latency is used to identify debt limits for the number of concurrent storage operations issued to the memory drives. The storage processor may issue additional storage operations to the memory devices when the number of storage operations is within the debt limit. Storage operations may be deferred when the number of storage operations is outside the debt limit.

Abstract: Cache lines are identified that provide incorrect data for read requests. The cache lines are invalidated before the incorrect data causes processing failure conditions. The cache lines providing incorrect data may be detected according to a number of the same read requests to the same cache lines. The cache lines may also be identified according to an amount of time between the same read requests to the same cache lines. The same read requests to the same cache lines may be identified according to associated start addresses and address lengths.

Abstract: A storage system creates an abstraction of flash Solid State Device (SSD) media allowing random write operations of arbitrary size by a user while performing large sequential write operations of a uniform size to an SSD array. This reduces the number of random write operations performed in the SSD array and as a result increases performance of the SSD array. A control element determines when blocks from different buffers should be combined together or discarded based on fragmentation and read activity. This optimization scheme increases memory capacity and improves memory utilization and performance.

Abstract: A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.

Abstract: A circuit card for a data processing system includes a printed circuit board (PCB) and a carrier. The PCB includes opposing sides parallel to a mounting direction when the PCB is installed to a cage. The carrier is attached to the PCB and includes at least one guiding member offset from a normal direction of the PCB and guiding installation of the PCB in the cage. The cage includes a plurality of support plates extending along a first direction and aligned along a second direction perpendicular to the first direction of the cage to define a plurality of air flow channels. When the circuit card is mounted to one of the support plates by engaging the guiding member to the support plate, the PCB is offset from the support plate and located right in the air flow channel without being obstructed by the support plate.

Abstract: A storage access system provides consistent memory access times for storage media with inconsistent access latency and reduces bottlenecks caused by the variable time delays during memory write operations. Data is written iteratively into multiple different media devices to prevent write operations from blocking all other memory access operations. The multiple copies of the same data then allow subsequent read operations to avoid the media devices currently servicing the write operations. Write operations can be aggregated together to improve the overall write performance to a storage media. A performance index determines how many media devices store the same data. The number of possible concurrent reads varies according to the number of media devices storing the data. Therefore, the performance index provides different selectable Quality of Service (QoS) for data in the storage media.

Abstract: A cluster of storage control members connect different clients to different storage disks. Connection path information between the different clients and disks is discovered and distributed to the storage cluster members. The connection path information is then used to maintain coherency between tiering media contained in the different storage cluster members. Unique Small Computer System Interface (SCSI) identifiers may be associated with the different connection paths to uniquely identify particular storage disks connected to the clients.

Abstract: A fiber channel network is configured into different zones. A first zone of the fiber channel network is configured with an initiator port, a first virtual port for a first physical port on a storage proxy, and a first virtual port for a second physical port on the storage proxy. A second zone of the fiber channel network is configured with a storage target port, a second virtual port for the first physical port on a storage proxy, and a second virtual port for the second physical port on the storage proxy. The virtual ports configured on the storage proxy increase the amount of bandwidth in the fiber channel available for asymmetric data transfers.

Abstract: Storage of digital data in non-volatile media such as NAND FLASH needs to take account of the errors in data retrieved from the memory. The error rate tends to increase with the number of write/erase cycles of a cell of memory and with the time that the data has been stored. To achieve a very low uncorrected bit error rate (UBER) a substantial amount of redundancy data needs to be stored for error correction purposes. A method and apparatus is disclosed where a first redundancy data is represented by a second redundancy data computed from the first redundancy data. The first redundancy data may not be stored and is reconstructed from the stored data using a same generation procedure as previously used. The reconstructed estimate of the first redundancy data is corrected by the second redundancy data, and is used to correct the underlying data.

Abstract: A storage proxy receives different abstracted memory access requests that are abstracted from the original memory access requests from different sources. The storage proxy reconstructs the characteristics of the original memory access requests from the abstracted memory access requests and makes prefetch decisions based on the reconstructed characteristics. An inflight table is configured to identify contiguous address ranges formed by an accumulation of sub-address ranges used by different abstracted memory access requests. An operation table is configured to identify the number of times the contiguous address ranges are formed by the memory access operations. A processor is then configured to prefetch the contiguous address ranges for certain corresponding read requests.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: A storage proxy loads cache lines with data from a storage device. Storage access requests are received from an initiator and directed to the storage device. The storage proxy provides the data from the cache lines in response to cache hits on the cache lines, and provides the data from the storage device in response to cache misses on the cache lines. Hit access times are identified for the cache lines in response to the cache hits and miss access times are identified for the storage device in response to cache misses. Data in the cache lines is updated with data from the storage device based on the hit access times and the miss access times associated with the cache lines.