Abstract: A Read only memory (ROM) with minimum leakage includes a ROM array including a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. The drain of the first transistor is electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal.

Abstract: Two floating gate devices are arranged in a redundant configuration in a non-volatile memory (NVM) of a Radio Frequency Identification (RFID) tag such that stress induced leakage current (SILC) or other failures do not result in a complete loss of memory storage. The redundant NVM may be arranged as a series configuration, a parallel configuration, a single-ended device, a differential device, a simple logic circuit function, and/or a complex logic circuit function.

Abstract: A configurable memory device includes an array of configurable memory units arranged into rows and columns. The configurable memory unit includes a memory cell comprising a first storage element configured to store a first value and a second storage element configured to store a second value. The memory unit can be either a single-ended or a differential configuration. In the single-ended configuration, the stored value of each storage element is interpreted as one bit. In the differential configuration, the stored first and second values of the storage elements are interpreted as a differential single bit. An external control signal determines in which configuration the unit is in.

Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate and a four transistor storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

Abstract: Integrated circuits may include at least an instruction processor and input-output subsystems. Each input-output subsystem includes a wrapper circuit a wrapper circuit controlled by the instruction processor. The wrapper circuit includes two or more scan registers, where a data value stored in each scan register can be shifted out for analysis. The wrapper circuit also includes two or more update registers to transfer stored data values between itself and an associated scan register. The wrapper circuit also includes a set of combinatorial logic coupled to the scan registers, the update registers and the instruction test processor, wherein at least two I/Os of the plurality of I/Os but less than all of the plurality of I/Os couple to an external tester.

Abstract: A computer-implemented method for creating an integrated circuit, IC, test engine for testing a proposed IC memory array using new memory structural model. An IC designer inputs the number of words that can be stored and a column multiplexer ratio in a proposed IC memory array. A selection of one or more procedures is made from a library of computer-readable procedures. Each of the procedures is to produce one or more structural primitives that describe certain physical layout features of the proposed IC memory array, without analyzing a CAD layout file of the proposed IC memory array. The library of procedures as a whole translates between a physical model of a family of IC memory arrays and a user interface model of the family. A data background, DB, pattern is produced to be used by the test engine in testing the proposed IC memory array. This is done by executing the selected one or more procedures, wherein these procedures take as input the received number of words and column multiplexer size.

Abstract: A Schottky junction diode device having improved performance is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped to a second conductivity type opposite that of the first conductivity type. A region of metal-containing material is disposed over the first well to form a Schottky junction at an interface between the region of metal-containing material and the first well. In one embodiment, a first well contact is disposed in a portion of the first well. A second well is disposed over the substrate wherein the second well includes a material doped to the first conductivity type. In one embodiment, the first well and the second well are not in direct contact with one another.

Abstract: Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.

Abstract: Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.

Abstract: A configurable memory device includes an array of configurable memory units arranged into rows and columns. The configurable memory unit includes a memory cell comprising a first storage element configured to store a first value and a second storage element configured to store a second value. The memory unit can be either a single-ended or a differential configuration. In the single-ended configuration, the stored value of each storage element is interpreted as one bit. In the differential configuration, the stored first and second values of the storage elements are interpreted as a differential single bit. An external control signal determines in which configuration the unit is in.

Abstract: Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor substrate. The first injection current flows through the first gate dielectric to establish a first amount of electrical charge on the gate electrode. The electronic circuitry also includes a second transistor having a second gate dielectric located between the gate electrode and the semiconductor substrate. A band-to-band tunneling current flows between valence and conduction bands of the second transistor to create a second injection current that flows through the second gate dielectric to establish the first amount of electrical charge on the gate electrode. Non-volatile memory cell circuits having the above described circuitry are also described.

Abstract: Methods and structure for fault tolerant Non Volatile Memory (NVM) devices are provided. Readings of selected memory cells are compared to two thresholds above and below a neutral value. Consistency of comparison outputs is used to determine a good or bad reading. Parity bit correction can be used to correct bad readings.

Abstract: Two floating gate devices are arranged in a redundant configuration in a non-volatile memory (NVM) such that stress induced leakage current (SILC) or other failures do not result in a complete loss of memory storage. The redundant NVM may be arranged as a series configuration, a parallel configuration, a single-ended device, a differential device, a simple logic circuit function, a complex logic circuit function, and/or as part of an RFID tag system.

Abstract: A method and apparatus are described in which an optimal configuration of memory instances is determined. The optimal configuration of memory instances to be fabricated with built-in repair capacity and memory instances that are non-repairable may provide a maximum number of good chip dies per wafer. An amount of memory instances to be fabricated with built-in repair capacity as well as a remaining amount of memory instances to be fabricated without any built-in repair components in the integrated circuit design is determined relative to achieving the maximum number of good chip dies per wafer for a given defect density and wafer area. The amount of good dies produced per fabricated wafer for a populated amount of memories with built-in repair components is determined to be between an amount established by a minimum limit for the die area up to the amount established by a maximum limit for the die area.

Abstract: Integrated circuits may include at least an instruction processor and input-output subsystems. Each input-output subsystem includes a wrapper circuit a wrapper circuit controlled by the instruction processor. The wrapper circuit includes two or more scan registers, where a data value stored in each scan register can be shifted out for analysis. The wrapper circuit also includes two or more update registers to transfer stored data values between itself and an associated scan register. The wrapper circuit also includes a set of combinatorial logic coupled to the scan registers, the update registers and the instruction test processor, wherein at least two I/Os of the plurality of I/Os but less than all of the plurality of I/Os couple to an external tester.

Abstract: The present disclosure provides a Non-Volatile Memory (NVM) cell and programming method thereof. The cell can denote at least two logic levels. The cell has a read-transistor with a floating gate, and Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor. The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased with a first gate bias voltage such that the BTBT device is in accumulation, to set at least one of the logic levels. A first electrode is coupled to bias the BTBT device with a first bias voltage that is higher than the first threshold voltage. The first bias voltage is controlled such that the BTBT device is in accumulation during a write operation. The injected amount of charge on the floating gate is determined by the first bias voltage.

Abstract: Timing test circuits, including programmable strobe and clock generators, may include at least two DLLs having differing numbers of delay elements thereby producing many timing signals having various phase relationships. A detector circuit can generate many different timing intervals as may be defined by independently selected events in signals arising from both of the DLLs.

Abstract: An apparatus for a volatile latch circuit. The volatile latch circuit may have a master latch sub circuit coupled to a slave latch sub circuit. The slave latch sub circuit maintains the logic state stored by the volatile latch circuit. The slave sub circuit may connect to a first power trace that continuously provides a first voltage potential to the slave latch sub circuit even during a sleep mode. The master latch sub circuit may connect to a second power trace that provides a second voltage potential to the master latch sub circuit that is switchably turned off during the sleep mode.

Abstract: Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I/Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, a Device Interface Board (DIB) that includes resistors between the chip and the external tester, and various tests performed on the I/Os by the on-chip testing logic and external testing unit facilitated through the DIB.

Abstract: Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, and various tests performed on the I-Os by the on-chip testing logic, the test vector patterns supplied by the external testing unit.