Abstract: A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell design with smaller, single-height cells for high-density applications. The single-height cells may be used where possible and higher-drive dual-height basic cells where larger transistors are desired. Other multiple height cells may also be included if even more current is desirable. The power rail may include conductors of varying width.

Abstract: Various apparatuses and methods in which a dual-polarity non-volatile memory cell includes a sense mode component and a charge mode component. The sense mode component communicates information stored in the dual-polarity non-volatile memory cell during a read operation. The charge mode component facilitates storing of the information stored in the dual-polarity non-volatile memory cell. The charge mode component includes a first coupling capacitor and a second tunneling capacitor in a first well, and a first tunneling capacitor and a second coupling capacitor in a second well.

Abstract: In general, a method, apparatus, and system determine the allocation of the one or more redundant components while fault testing the memory. In an embodiment of an apparatus, one or more memories and one or more processors are located on a single chip. Each memory has one or more redundant components associated with that memory. The one or more redundant components include at least one redundant column. The one or more processors contain redundancy allocation logic having an algorithm. The algorithm determines the allocation of the one or more redundant components to repair one or more defects detected in the one or more memories while fault testing the memory.

Abstract: A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material.

Abstract: Various methods and apparatuses are described in which a volatile latch circuit. The volatile latch circuit may have a master latch sub circuit coupled to a slave latch sub circuit. The slave latch sub circuit maintains the logic state stored by the volatile latch circuit. The slave sub circuit may connect to a first power trace that continuously provides a first voltage potential to the slave latch sub circuit even during a sleep mode. The master latch sub circuit may connect to a second power trace that provides a second voltage potential to the master latch sub circuit that is switchably turned off during the sleep mode.

Abstract: Methods and apparatuses in which a ROM memory array has virtual-grounded source lines programmed in layer physically higher than the diffusion layer. The ROM memory array may include a diffusion layer, one or more virtual-grounded source lines, and one or more bit lines. At least one of the virtual-grounded source lines is programmed with a layer physically higher than the diffusion layer.

Abstract: Various apparatuses and methods are shown in which an integrated circuit includes a dual-polarity non-volatile memory cell and a test circuit. The test circuit has a bias voltage generator and a first switch. The bias voltage generator couples to the dual-polarity non-volatile memory cell via the first switch.

Abstract: Various methods, apparatuses, and systems in which a read only memory is arrayed in a multiple rows and columns. A first column of memory cells is organized into groups of memory cells including a first group of memory cells and a second group of memory cells. A first source line connects to one or more memory cells in the first group of memory cells. The first source line changes its voltage state during a read operation on one or more bit cells in the first group. A second source line connects to one or more memory cells in the second group of memory cells. The second source line maintains its voltage state during the read operation.

Abstract: Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a first group of memory cells at the substantially the same time. The noise reduction circuit performs a sense operation on a second group of memory cells at substantially the same time. The noise reduction circuit has timing circuitry to sense the second group of memory cells after the sense of the first group initiates but prior to the completion of the sense operation on the first group of memory cells.

Abstract: Various apparatuses and methods in which an integrated circuit includes a non-volatile memory cell and a keep mode circuit. The non-volatile memory cell has a charge storage component. The keep mode circuit has a storage device and a keep mode switch. The storage device receives information stored in the non-volatile memory cell. The keep mode switch connects the storage device to the non-volatile memory cell in order to apply a static bias voltage across the charge storage component to restrict charge-loss to a predetermined level.

Abstract: A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell design with smaller, single-height cells for high-density applications. The single-height cells may be used where possible and higher-drive dual-height basic cells where larger transistors are desired. Other multiple height cells may also be included if even more current is desirable. The power rail may include conductors of varying width.

Abstract: A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material.

Abstract: A multiple bank memory array includes a combined memory array, an X-decoder, a first word-line driver, a second word-line driver, a reference column, a Y-multiplexer and pre-charging circuit, a sense amplifier and input/output circuit, and control and pre-coding logic. Signals are received and applied to the combined memory array and the other components via the control and pre-decode logic and the input/output circuit. The control and pre-decode logic receives control signals to control and address the combined memory array, and uses a single bit for two dimensional decoding. This architecture for multiple bank memory cell arrays a novel technique for word-line banking using tilable strap cells in a first embodiment that provides a combined array, does not require routing and eliminates redundant reference columns.

Abstract: A system and method is provided for bit line sharing in a memory device. Adjacent memory cells are configured to share a bit line and are accessed with separate word lines as an odd and even plane. Bit line sharing reduces the number of Y-multiplexors and I/O circuitry required by about two-fold, and provides power savings by reducing the number of bit lines pre-charged.

Abstract: A method, system, and apparatus exist which couple a first group of non-redundant memory columns to a non-redundant input-output circuit and couple a second group of redundant memory columns to a redundant input-output circuit. A fewer amount of memory columns exist in the second group of redundant memory columns than in the first of non-redundant memory columns. A first fuse indicates whether one or more memory columns are defective in a group of non-redundant memory columns coupled to the non-redundant input output circuit. Also, a second fuse couples to a first circuit. The first circuit identifies which sub-input circuit is coupled to the one or more defective memory columns.

Abstract: An metal programmable integrated circuit apparatus and method of manufacture and design using elevated metal layers for design-specific customization. The lower metal layer are used to form core cells and to provide power and clocking signals to the core cells. These core cell are customizable by the designer using only the upper metal layers. This new architecture allows faster turn-around time and fewer masks while keeping the time-to-market advantages of gate array structures.

Abstract: A method, system, and apparatus exist which couple a first group of non-redundant memory columns to a non-redundant input-output circuit and couple a second group of redundant memory columns to a redundant input-output circuit. A fewer amount of memory columns exist in the second group of redundant memory columns than in the first group of non-redundant memory columns. A first fuse indicates whether one or more memory columns are defective in a group of non-redundant memory columns coupled to the non-redundant input output circuit. Also, a second fuse couples to a first circuit. The first circuit identifies which sub-input-output circuit is coupled to the one or more defective memory columns.

Abstract: An apparatus and method in which a single fuse is asserted in a memory bank having a redundancy memory column structure. The assertion of the single fuse causes two or more of the input-output circuits to shift away from a primary memory column to a substitute memory column.

Abstract: A self-timed write control memory device minimizes the memory cycle time for the cells of the array. The self-timed write control memory device preferably comprises an X-decoder, a word-line driver, a memory cell array, control logic, pre-charge circuits, sense amplifiers, a reference decoder, and a reference word-line driver. The memory device preferably further includes a first reference cell, a second reference cell or logic, a first reference column, a second reference column and a reference sense amplifier. The first reference cell is preferably used for detection of read cycle completion and the second reference cell or logic is used for detection of write cycle completion. The output of the first reference cell and second reference cell are preferably coupled to inputs of a unique reference sense amplifier.

Abstract: A multiple bank memory array includes a combined memory array, an X-decoder, a first word-line driver, a second word-line driver, a reference column, a Y-muitiplexer and pre-chargingz circuit, a sense amplifier and input/output circuit, and control and pre-coding logic. Signals are received and applied to the combined memory array and the other components via the control and pre-decode logic and the input/output circuit. The control and pre-decode logic receives control signals to control and address the combined memory array, and uses a single bit for two dimensional decoding. This architecture for multiple bank memory cell arrays a novel technique for word-line banking using tillable strap cells in a first embodiment that provides a combined array, does not require routing and eliminates redundant reference columns.