Patents Assigned to Vishay Intertechnology
  • Patent number: 6892443
    Abstract: A high precision power resistor having the improved property of reduced resistance change due to power is disclosed. The resistor includes a substrate having first and second flat surfaces and having a shape and a composition; a resistive foil having a low TCR of about 0.1 to about 1 ppm/° C. and a thickness of about 0.03 mils to about 0.7 mils cemented to one of the flat surfaces with a cement, the resistive foil having a pattern to produce a desired resistance value, the substrate having a modulus of elasticity of about 10×106 psi to about 100×106 psi and a thickness of about 0.5 mils to about 200 mils, the resistive foil, pattern, type and thickness of cement, and substrate being selected to provide a cumulative effect of reduction of resistance change due to power. The present invention also provides for a method of producing a high precision power resistor.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: May 17, 2005
    Assignee: Vishay Intertechnology
    Inventors: Joseph Szwarc, Reuven Goldstein
  • Publication number: 20050083170
    Abstract: A high precision power resistor having the improved property of reduced resistance change due to power is disclosed. The resistor includes a substrate having first and second flat surfaces and having a shape and a composition; a resistive foil having a low TCR of about 0.1 to about 1 ppm/° C. and a thickness of about 0.03 mils to about 0.7 mils cemented to one of the flat surfaces with a cement, the resistive foil having a pattern to produce a desired resistance value, the substrate having a modulus of elasticity of about 10×106 psi to about 100×106 psi and a thickness of about 0.5 mils to about 200 mils, the resistive foil, pattern, type and thickness of cement, and substrate being selected to provide a cumulative effect of reduction of resistance change due to power. The present invention also provides for a method of producing a high precision power resistor.
    Type: Application
    Filed: October 18, 2004
    Publication date: April 21, 2005
    Applicant: Vishay Intertechnology
    Inventors: Joseph Szwarc, Reuven Goldstein
  • Patent number: 6880234
    Abstract: A method for manufacturing a thin film negative temperature coefficient thermistor is disclosed. The method includes selecting a negative temperature coefficient of resistance versus temperature curve, selecting a mixture of metal film materials to provide the negative temperature coefficient of resistance curve while maintaining a desired physical size, and depositing the mixture of metal film materials on a substrate.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: April 19, 2005
    Assignee: Vishay Intertechnology, Inc.
    Inventor: Javed Khan
  • Patent number: 6880233
    Abstract: A fast heat rise resistor comprising a substrate, a foil bridge on the surface of the substrate, the foil bridge having an elevated portion and a contact portion, the elevated portion above the substrate, the contact portion in contact with the substrate, a conductive layer attached to the contact portion of said foil bridge. The activation energy and/or response time is reduced as the foil bridge is suspended over the substrate. Another aspect of the invention include a method of manufacturing the foil bridge and application to autoignition vehicle airbags.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: April 19, 2005
    Assignee: Vishay Intertechnology, Inc.
    Inventors: George V. Gerber, Anthony E. Troianello, Haim Goldberger
  • Patent number: 6876061
    Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate).
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: April 5, 2005
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6873028
    Abstract: A chip resistor comprising a substrate having opposite parallel symmetrical first and second surfaces, a central longitudinal plane of symmetry, separate and spaced first and second resistive layers on the first and second surfaces. The resistive layers are electrically connected in parallel to each other and the first and second surfaces of the substrate are symmetrically located with respect to and equidistant from a central longitudinal plane. Thus, when electrical current passes through the resistive layers, a temperature distribution within the substrate will be substantially symmetrical about the central longitudinal plane of the substrate for eliminating thermal bending thereof. The splitting of the surge current between two resistive layers results in the lower temperature in each resistive layer when compared with the temperature in the single resistive layer of the prior art chip resistor loaded by the same current.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: March 29, 2005
    Assignee: Vishay Intertechnology, Inc.
    Inventor: Michael Belman
  • Publication number: 20040159162
    Abstract: An improved strain gage is disclosed. The strain gage includes a semi-rigid substrate having a thickness of about 1 to about 30 mils, a resistive strain sensitive foil bonded to the semi-rigid substrate for providing a resistance varying with strain associated with a surface to which the strain gage is attached, and a first and a second terminal operatively connected to the resistive strain sensitive foil.
    Type: Application
    Filed: February 19, 2003
    Publication date: August 19, 2004
    Applicant: Vishay Intertechnology
    Inventors: Thomas Patrick Kieffer, Robert Barry Watson, Sharon Lee Karcher Harris
  • Publication number: 20040150505
    Abstract: A high precision power resistor having the improved property of reduced resistance change due to power is disclosed. The resistor includes a substrate having first and second flat surfaces and having a shape and a composition; a resistive foil having a low TCR of about 0.1 to about 1 ppm/° C. and a thickness of about 0.03 mils to about 0.7 mils cemented to one of the flat surfaces with a cement, the resistive foil having a pattern to produce a desired resistance value, the substrate having a modulus of elasticity of about 10×106 psi to about 100×106 psi and a thickness of about 0.5 mils to about 200 mils, the resistive foil, pattern, type and thickness of cement, and substrate being selected to provide a cumulative effect of reduction of resistance change due to power.
    Type: Application
    Filed: January 22, 2004
    Publication date: August 5, 2004
    Applicant: Vishay Intertechnology
    Inventors: Joseph Szwarc, Reuven Goldstein
  • Publication number: 20040100356
    Abstract: A high precision power resistor having the improved property of reduced resistance change due to power is disclosed. The resistor includes a substrate having first and second flat surfaces and having a shape and a composition; a resistive foil having a low TCR of about 0.1 to about 1 ppm/° C. and a thickness of about 0.03 mils to about 0.7 mils cemented to one of the flat surfaces with a cement, the resistive foil having a pattern to produce a desired resistance value, the substrate having a modulus of elasticity of about 10×106 psi to about 100×106 psi and a thickness of about 0.5 mils to about 200 mils, the resistive foil, pattern, type and thickness of cement, and substrate being selected to provide a cumulative effect of reduction of resistance change due to power. The present invention also provides for a method of producing a high precision power resistor.
    Type: Application
    Filed: November 25, 2002
    Publication date: May 27, 2004
    Applicant: Vishay Intertechnology
    Inventors: Joseph Szwarc, Reuven Goldstein
  • Patent number: 6727798
    Abstract: The present invention provides for a flip chip resistor having a substrate having opposite ends, a pair of electrodes formed from a first electrode layer disposed on the opposite ends of the substrate, a resistance layer electrically connecting the pair of electrodes, a protective layer overlaying the resistance layer, and a second electrode layer overlaying the first electrode layer and at least a portion of the protective layer. The present invention provides for higher reliability performance and enlarging the potential soldering area despite small chip size.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: April 27, 2004
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Leonid Akhtman, Sakaev Matvey
  • Publication number: 20040041278
    Abstract: The present invention provides for a flip chip resistor having a substrate having opposite ends, a pair of electrodes formed from a first electrode layer disposed on the opposite ends of the substrate, a resistance layer electrically connecting the pair of electrodes, a protective layer overlaying the resistance layer, and a second electrode layer overlaying the first electrode layer and at least a portion of the protective layer. The present invention provides for higher reliability performance and enlarging the potential soldering area despite small chip size.
    Type: Application
    Filed: May 19, 2003
    Publication date: March 4, 2004
    Applicant: Vishay Intertechnology, Inc.
    Inventors: Leonid Akhtman, Sakaev Matvey
  • Patent number: 6680668
    Abstract: A fast heat rise resistor comprising a substrate, a foil bridge on the surface of the substrate, the foil bridge having an elevated portion and a contact portion, the elevated portion above the substrate, the contact portion in contact with the substrate, a conductive layer attached to the contact portion of said foil bridge. The activation energy and/or response time is reduced as the foil bridge is suspended over the substrate. Another aspect of the invention include a method of manufacturing the foil bridge and application to autoignition vehicle airbags.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: January 20, 2004
    Assignee: Vishay Intertechnology, Inc.
    Inventors: George V. Gerber, Anthony E. Troianello, Haim Goldberger
  • Patent number: 6671945
    Abstract: A fast heat rise resistor comprising a substrate, a foil bridge on the surface of the substrate, the foil bridge having an elevated portion and a contact portion, the elevated portion above the substrate, the contact portion in contact with the substrate, a conductive layer attached to the contact portion of said foil bridge. The activation energy and/or response time is reduced as the foil bridge is suspended over the substrate. Another aspect of the invention include a method of manufacturing the foil bridge and application to autoignition vehicle airbags.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: January 6, 2004
    Assignee: Vishay Intertechnology, Inc.
    Inventors: George V. Gerber, Anthony E. Troianello, Haim Goldberger
  • Patent number: 6669435
    Abstract: A system, method, and apparatus, for resistor tube feeding is disclosed. A tube magazine comprising a length of tubing and adapted for receiving precision resistor cores and compressed air is disclosed. The tube magazine may be connected to a laser spiraller and a terminal welder. The process of filling the tube magazine may be electronically controlled.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: December 30, 2003
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Thomas L. Bertsch, Daryl J. Klataske
  • Patent number: 6621143
    Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: September 16, 2003
    Assignee: Vishay Intertechnology, Inc
    Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
  • Patent number: 6621142
    Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: September 16, 2003
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
  • Patent number: 6562647
    Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate).
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: May 13, 2003
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6538300
    Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: March 25, 2003
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
  • Publication number: 20020185710
    Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate).
    Type: Application
    Filed: May 28, 2002
    Publication date: December 12, 2002
    Applicant: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6451074
    Abstract: A conductive polymer capacitor includes an anode formed from a porous metal body having an anode lead extending therefrom. A dielectric layer is formed by oxidizing a surface of the anode. A solid electrolyte is formed on the dielectric layer and includes first and second polymer layers. The second conductive polymer layer includes a polyaniline layer formed by dipping the metal body having the first conductive layer thereon into a solution of doped polyaniline dissolved in an organic solvent.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: September 17, 2002
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Alexander Bluvstein, Gerovich Vera, Alexander Osherov, Vitaly Strokhin
  • Patent number: 5248298
    Abstract: An insert is provided to be attached to a shield on a surgical trocar obturator handle. The insert is actuated by the surgical trocar cannula handle so that it causes the shield to expose the sharpened obturator tip after insertion of the obturator and shield within the cannula. After usage, the insert is deactivated so that the shield again covers the obturator. The obturator can then be removed from the cannula handle and obturator shield, and the obturator handle can be discarded safely.
    Type: Grant
    Filed: April 16, 1992
    Date of Patent: September 28, 1993
    Assignee: Ethicon, Inc.
    Inventors: James Bedi, Steven Annunziato