Abstract: A heterojunction bipolar transistor with self-aligned features having a self-aligned dielectric sidewall spacer disposed between base contact and emitter contact, and self-aligned base mesa aligned relative to self-aligned base contact. The base contact is self-aligned relative to the self-aligned dielectric sidewall spacer providing a predetermined base-to-emitter spacing thereby. The emitter may be an n-type, InP material; the base can be a p-type InGaAs material, possibly carbon-doped. The fabrication method includes forming a emitter electrode on an emitter layer; using the emitter contact as a mask, anisotropically etching the emitter exposing the base layer; forming a self-aligned dielectric sidewall spacer upon the emitter and base; self-alignedly depositing a self-aligned base electrode; using the self-aligned base electrode as a mask, anisotropically etching the base layer to expose the subcollector; and depositing a collector electrode on the subcollector layer.

Abstract: An optical cross connect with simultaneous correction of multiple mirror angles to achieve desired output power. In one embodiment beam offset and pointing angle are changed and output power is measured to determine changes to mirror angles.

Abstract: Actuator-controlled mirrors with a Z-stop mechanism to reduce an undesired translational motion of the mirrors.

Abstract: A multidimensional forward error correction system. Transmitted data is encoded by an encoder in multiple dimensions. The decoding of received data by a decoder is performed in multiple passes, with corrected data rewritten into memory. The encoder in one embodiment comprises a parallel column decoder and multiple row encoders encoding a (255, 239) BCH code.

Abstract: A low temperature aluminum planarization process. Vias, including high aspect ratio vias, are filled using a liner layer, a seed layer, and a fill layer. The device associated with the via is exposed to a reactive gas prior to applying the fill layer to the device.

Abstract: A multidimensional forward error correction system. Transmitted data is encoded by an encoder in multiple dimensions. The decoding of received data by a decoder is performed in multiple passes, with corrected data rewritten into memory. The encoder in one embodiment comprises a parallel column decoder and multiple row encoders encoding a (255, 239) BCH code.

Abstract: A clock recovery unit is used to recover a clock signal from a transmitted data signal. The clock recovery unit includes a phase locked loop (PLL) circuit and a frequency detection circuit. The frequency detection circuit includes a digital phase tracking circuit (DPTC), which uses a rotational phase shifter to shift phase of a variable clock signal from a voltage controlled oscillator in the PLL circuit, in discrete amounts from 0 to 360 degrees, depending on a digital input code provided by a digital accumulator, which receives up or down count signals from a phase comparator. The shifted variable clock signal is provided to a phase/frequency detector, which provides an output to a glitch suppressor to suppress small phase differences prior to providing the output to the PLL circuit. When the frequency difference between the variable clock signal and the reference clock signal is large, the phase/frequency detector drives the frequency in the correct direction.

Abstract: A semiconductor device package adapted for use with high frequency signals and/or coaxial connections. The package has an angled coaxial input shielded by a plurality of vias. In one embodiment the coaxial input is orthogonal to a leadframe, and the coaxial input is matched to a transmission line on the leadframe.

Abstract: A Loss Of Signal (LOS) circuit in an opto-electronic receiver circuit. The LOS circuit includes a current to voltage converter and a comparator circuit. The current to voltage circuit receives a current signal including a DC current signal component from a photodetector circuit included in the opto-electronic receiver. The current to voltage receiver generates a voltage signal in response to the DC current signal. The comparator circuit receives the voltage signal from the current to voltage circuit and generates a LOS signal from the voltage signal by comparing the voltage signal to a reference voltage signal.

Abstract: A housing that includes separated and removable transmitter modules, and common receiver circuitry. The receiver is common to all modules, but the modules can be removed and replaced to allow different frequencies and the like. Each module also includes its own heat handling mechanism such as a heat sink.

Abstract: An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock.

Abstract: A semi-parallel forward error correction system. In one embodiment the forward error correction system includes a semi-parallel Reed-Solomon encoder and a semi-parallel Reed-Solomon decoder. Information symbols comprised of bytes are provided eight bytes in parallel to an encoder which in parallel forms eight bytes of a nonsystematic code word. On decoding, a code word is provided to a time multiplexed syndrome generator and key equation solver. An error locator polynomial from the key equation solver and the syndromes from the syndrome generator are provided to an error location and error magnitude unit, which includes a plurality of polynomial evaluator units which process an error locator polynomial in parallel.

Abstract: A drive circuitry that drives a vertical cavity surface emitting laser is provided. The drive circuitry includes a modulator, a negative peak timer and a limiter. The negative peak timer causes the modulator to rapidly decrease the magnitude of the output signal of the modulator to dissipate charge stored on the laser. Thus, the vertical cavity surface emitting laser quickly turns off.

Abstract: Techniques and devices for using fibers that are angle-polished to reduce the adverse effects of optical reflection. Each fiber is mounted so that the longitudinal direction of the fiber core forms an angle with respect to an optical axis of a device along which an optical beam is coupled to or from the angle-polished end facet of the fiber.

Abstract: Techniques for optically sampling the output of a Mach-Zehnder electro-optic modulator without interfering the output optical signal.

Abstract: A circuit includes a differential amplifier providing a differential signal to a voltage follower. The output of the voltage follower is fed back through resistors to an additional differential amplifier to the respective inputs to the voltage follower. The feedback is negative at low frequencies and less negative or positive about the clock frequency.

Abstract: Methods and apparatus for providing precision on-chip termination of transmission lines are provided which enable the termination of transmission lines using on-chip resistors configured into networks, which have resistances related to the resistance of an external reference resistor. The external reference resistor is used to configure an on-chip reference resistor network so that it has a resistance related to the resistance of the external reference resistor. Termination resistor networks are then configured so that their resistances bear a predetermined relationship to the resistance of the on-chip reference resistor network. In one embodiment the resistance of each of the termination resistor networks is substantially the same as the characteristic impedances of each of the transmission lines.

Abstract: A loss of signal detection circuit using Gilbert mixers. A differential input signal is provided to an input Gilbert mixer. Reference signals are provided to a reference Gilbert mixer. The two Gilbert mixers pull reference lines in opposing directions such that a one line is higher than another line when the differential input signal provides valid data.

Abstract: A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL based clock recovery unit in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.

Abstract: A nonplanar substrate surface is substantially uniformly planarized by a chemical mechanical planarization (CMP) process. The CMP process uses multiple sources of slurry delivered in between a slurry distribution screen and a slurry membrane of the CMP apparatus. The multiple slurry sources have differing chemical and physical compositions, and are delivered to different locations along the membrane. The slurries bleed into each other during polish to form a radially-variable, slurry abrasiveness concentration gradient. As a result, there are areas with a greater abrasiveness concentration of slurry, and hence a greater frictional contact. The slurry flow rate and concentration is adjusted along the wafer surface according to the non-uniformly planar areas of the wafer. Consequently, uniform planarization is substantially achieved.