Abstract: The speed and stability of a 4T static RAM cell (10) comprising cross-coupled inverters with two driver transistors (18, 20) and two pass-gate transistors (14,16) are improved by replacing the driver transistors with a modified driver element (33, 35), comprising at least two transistors (18, 18') having common gates and common sources and with a resistor (42) connecting the drains.

Abstract: A dependable ohmic contact with consistently low specific contact resistance (<1.times.10.sup.-6 .OMEGA.-cm.sup.2) to n-type GaAs (10) is produced by a three or four step procedure. The procedure, which is employed following implantation to form doped regions in the GaAs substrate for contacting thereto, comprises:(a) adsorbing or reacting sulfur or a sulfur-containing compound (26) with the GaAs surface (10') at locations where the contact metal (28) is to be deposited;(b) forming a metal contact layer (28) on the treated portions of the GaAs surface;(c) optionally forming a protective layer (30) over the metal contact; and(d) heating the assembly (metal and substrate) to form the final ohmic contact. The surface treatment provides a lower specific contact resistance of the ohmic contact. Elimination of gold in the ohmic contact further improves the contact, since intermetallic compounds formed between gold and aluminum interconnects ("purple plague") are avoided.

Abstract: A direct shorting contact structure comprising a metal layer (18') makes ohmic contact with a source (10) and/or drain (12) region and with a gate electrode (22). The direct contact between source or drain and gate over the active region (16) reduces the area otherwise required for such contact and eliminates a second layer (24) of interconnection metallization otherwise required for such contact. The metal layer preferably comprises a first layer (18'a) of a material selected from the group consisting of gold-germanium, nickel-germanium, gold-germanium-nickel, molybdenum-germanium, and aluminum-germanium in ohmic contact with the source or drain region and with the gate electrode and a second layer (18'b) of a good electrically conductive, thermally stable, electromigration-resistant metal capable of providing good step coverage overlying the first layer. An example of the second layer is tungsten and its nitrides and silicides.

Abstract: A III-V semiconductor surface (10') of a III-V substrate (10) is provided with a thick dielectric layer (40), preferably comprising a composite nitride/oxide layer (40a/40b). A layer of comparatively thin silicon nitride layer (40a) is formed on the substrate and a comparatively thicker silicon dioxide layer (40b) is formed thereover. The composite dielectric layer acts as a good ion absorber during ion implantation (54), thereby masking the substrate from ions in undersirable locations. Further, the composite dielectric layer provides appropriate contrast for alignment marks, thereby reducing the number of masking steps and the amount of gate area in FETs otherwise required to compensate for potential misalignment. The composite dielectric layer affords surface protection, which not only keeps the semiconductor clean during processing, but also provides a cap during annealing.

Abstract: The speed and stability of a 4T static RAM cell (10) comprising cross-coupled inverters with two driver transistors, (18, 20) and two pass-gate transistors (14,16) are improved by replacing the driver transistors with a modified driver element (33, 35), comprising at least two transistors (18, 18') having common gates and common sources and with a resistor (42) connecting the drains.

Abstract: An integrated circuit, having applicability to GaAs circuitry, is disclosed for performing a current steering logic function. The integrated circuit comprises a switching circuit, a high impedance tail current source, and a pair of low impedances respectfully coupled to the tail current source through a respective one of the switching transistors. The resistors in the tail current source and in the load resistance are formed from sheet resistor material so that any process-induced variation in the resistivity of the sheet material causes a mutual but compensatory variation in both the load and current source resistors, maintaining a match between the current capability of the current source and the resistance of the loads. The follower circuit, on the other hand, comprises a low impedance FET and a follower current source having an active load whose current is primarily dependent on its threshold voltage.

Abstract: To decrease the time required to charge parasitic capacitances, and to thereby increase the maximum permissible switching frequency to which a logic circuit can respond, a GaAs device is disclosed having a current-injecting circuit that generates an initial pulse of capacitor-charging current during a "0"-to-"1" transition in the output state of a GaAs device. The pulse is sufficiently large to quickly charge the parasitic capacitances, and of sufficiently brief duration so that a minimum line width is permissible which is substantially equivalent to that which would be applicable in the absence of the current-injecting circuit.