Abstract: A video processing device includes a complexity estimation module to determine a first sum of variances metric and a first estimated picture encoding cost metric for a first picture of a video stream. The video processing device further includes a scene analysis module to determine a first threshold based on a first statistical feature for sum of variance metrics of a set of one or more pictures preceding the first picture in the video stream and a second threshold based on a second statistical feature for estimated picture encoding cost metrics of the set of one or more pictures. The scene analysis module further is to identify a scene change as occurring at the first picture based on the first sum of variances metric, the first estimated picture encoding cost metric, the first threshold, and the second threshold.

Abstract: A video processing device includes a data segmentation generator that receives a domain selection, n, and that segments input A/V data into n data blocks. An encryption processing device receives an encryption depth selection, k, and a range selection, m, and sequentially encrypts each of the n data blocks m times using k different keys to generate n encrypted data blocks. An output formatter generates encrypted A/V data from the n encrypted data blocks.

Abstract: A video processing device operates in an encoding mode when a mode selection signal has a first value and operates in a decoding mode when the mode selection signal has a second value. The encoding mode utilizes a plurality of function specific hardware engines that each perform a specific coding function and the decoding module utilizes at least one of the plurality of hardware engines.

Abstract: A system for encoding a video stream into a processed video signal that includes at least one image, includes a region identification signal generator for detecting a region of interest in the at least one image and generating a region identification signal when the pattern of interest is detected. An encoder section generates the processed video signal based on the operation of a plurality of encoding tools, each having at least one encoder quality parameter. The encoder section adjusts the at least one encoding quality parameter of at least one of the plurality of encoding tools in response to the region identification signal.

Abstract: A mixed-voltage circuit employs a higher-voltage transistor in series connection with a lower-voltage transistor. To protect the lower-voltage transistor from transient overvoltage events, a series of one or more diodes is connected between the current terminals (i.e., the source and drain terminals) of the lower-voltage transistor so as to limit the voltage across the lower-voltage transistor. This diode protection mechanism also may be provided between the gate terminal and a current terminal of the lower-voltage transistor so as to protect against an overvoltage event at the gate of the lower-voltage transistor. In this manner, the mixed-voltage circuit can provide the performance benefits of mixed use of lower-voltage and higher-voltage transistors while reducing the risk of damaging the lower-voltage transistors due to the use of the higher-voltage power supply needed for operation of the mixed-voltage circuit.

Abstract: A device for use in conjunction with a video processing device includes an adaptive filter for processing input pictures into selectively filtered pictures, based on a filter motion data. A deinterlacer selectively interpolates the selectively filtered pictures into selectively deinterlaced pictures, based on deinterlace motion data. A motion detector generates the filter motion data and the deinterlace motion data, based on detecting motion in the input pictures.

Abstract: A video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a plurality of vector processor units that generate a decoded video signal from the EDC data. The plurality of vector processing units are programmed via VPU instructions formatted to include a vector instruction portion, a scalar instruction portion, and a branching instruction portion.

Abstract: An entropy coding module is provided for use in a video encoder that encodes a video input signal based on a plurality of macroblocks derived from the video input signal. The entropy coding module includes an entropy coder that generates entropy encoded data from discrete transformed coefficients for the plurality of macroblocks. A neighbor management module stores neighbor data for at least one macroblock of the plurality of macroblocks for retrieval by the entropy encoder, when operating on at least one neighboring macroblock of the plurality of macroblocks.

Abstract: A processing system includes a memory module that includes a register space for storing a plurality of register data in a plurality of registers and secure access data corresponding to the register space. A register arbitration module operates to receive a request to access one of the registers from a client module; retrieve secure access data corresponding to the client to determine if the client is trusted; and to grant the request to access the register if the client is trusted. If the client is not trusted, the register arbitration module retrieves secure access data to determine if the register is non-secured for the client. The register arbitration module grants the request to access the register when the register is non-secured for the client.

Abstract: A video transcoder includes a deformatting module that generates a deformatted video signal based on a video signal in a source stereoscopic video format, and further based on device data that corresponds to a particular target device. A scaling module generates a scaled video signal, based on the deformatted video signal and further based on the device data. A formatting module generates a reformatted video signal in accordance with a target video format, based on the scaled video signal and further based on the device data.

Abstract: A technique for encoding and decoding video information uses a plurality of video processing modules (VPMs), whereby each video processing module is dedicated to a particular video processing function, such as filtering, matrix arithmetic operations, and the like. Information is transferred between the video processing modules using a set of first-in first-out (FIFO) buffers. For example, to transfer pixel information from a first VPM to a second VPM, the first VPM stores the pixel information at the head of a FIFO buffer, while the second VPM retrieves information from the tail of the FIFO buffer. The FIFO buffer thus permits transfer of information between the VPMs without storage of the information to a cache or other techniques that can reduce video processing speed.

Abstract: A video decoder includes an entropy decoding device that includes a first processor that generates entropy decoded (EDC) data from an encoded video signal, wherein the encoded video signal includes a plurality of video layers, wherein the entropy decoding device includes a slice dependency module that generates slice dependency data and wherein the first processor entropy decodes a selected subset of the plurality of video layers, based on the slice dependency data. A general video decoding device includes a second processor that generates a decoded video signal from the EDC data.

Abstract: A video processing device includes a content analyzer that receives a video signal and generates content recognition data based on the video signal, wherein the content recognition data is associated with at least one timestamp included in the video signal. A metadata search device generates time-coded metadata in response to content recognition data and in accordance with the at least one time stamp. A metadata association device generates a processed video signal from the video signal, wherein the processed video signal includes the time-coded metadata.

Abstract: A device includes a plurality of linear feedback shift registers, a counter having a counter value of a bit length, and a comparator to compare the counter value and an update value including bit values of bit positions of a first linear feedback shift register. The number of bit positions equal to the bit length of the counter value. A second linear feedback shift register to update based on the comparison.

Abstract: A method of operating a communications system includes generating a channel impulse response estimate based on a first received signal. The method includes selecting a precursor and a cyclic prefix length for a second received signal based on the channel impulse response estimate, a target cyclic prefix energy level, and a predetermined range of cyclic prefix lengths.

Abstract: A system and a method for simultaneous transmission of multiple media streams in a fixed bandwidth network are disclosed herein. The system is comprised of a central gateway media server and a plurality of client receiver units. The input media streams arrive from an external source and are then transmitted to the client receiver units in a compressed format. A state machine on the gateway media server detects if the network bandwidth is close to saturation. In one embodiment, the potential bandwidth saturation is measured by matching the time when the start of unit of media for each stream against the estimated transmission time for that unit.

Abstract: A processing system includes a memory module that includes a register space for storing a plurality of register data in a plurality of registers and secure access data corresponding to the register space. A register arbitration module operates to receive a request to access one of the registers from a client module; retrieve secure access data corresponding to the client to determine if the client is trusted; and to grant the request to access the register if the client is trusted. If the client is not trusted, the register arbitration module retrieves secure access data to determine if the register is non-secured for the client. The register arbitration module grants the request to access the register when the register is non-secured for the client.

Abstract: A system for transcoding a video signal into a transcoded video signal includes a drastic scene change detection module that detects a drastic scene change in a sequence of images, wherein the drastic scene change indicates a change in scene complexity. A transcoder section generates the transcoded video signal, wherein, when the drastic scene change is detected, a quality parameter is adjusted in at least one of the sequence of images.

Abstract: An apparatus includes a frequency mixer circuit configured to generate a baseband signal based on a local oscillator signal and a radio frequency signal. The apparatus includes a compensation circuit configured to generate a DC offset-compensated signal based on the baseband signal, a DC offset compensation signal, and a second signal. The DC offset compensation signal and the second signal have currents approximately equal in magnitude and opposite in direction. A current of the DC offset-compensated signal is substantially the same as a current of the baseband signal. The compensation circuit may include a DC digital-to-analog converter circuit configured to generate the DC offset compensation signal and the second signal based on a control signal.

Abstract: A method includes decompressing first compressed video data to provide uncompressed video data in a first order. The method includes compressing the uncompressed video data to provide second compressed video data in a second order. The decompressing and compressing are based on first and second compression rates, respectively. The first order may be based on fundamental blocks of a frame of video data and the second order is based on lines of the frame of video data. The compressing may include alternating compression of partial portions of a first line of uncompressed video data with compression of partial portions of at least a second line of uncompressed video data to thereby generate a first line of compressed video data corresponding to the first line of uncompressed video data and at least a second line of compressed video data corresponding to the second line of uncompressed video data.