Abstract: A video processing device includes a substrate. A plurality of ring oscillators generate a corresponding plurality of ring oscillator outputs. A control circuit generates power adjustment signals for adjusting at least one power supply voltage of the video processing device, based on the plurality of oscillator outputs.

Abstract: A video processing device includes a rate controller coupled to receive non-real time audio/video (A/V) data and buffer state feedback data from an input/output (I/O) device. The rate controller generates rate controlled non-real time A/V data from the non-real time A/V data and in response to the buffer state feedback data. A multiplexor multiplexes the rate controlled non-real time A/V data with real-time A/V data to generates multiplexed A/V data for input to the I/O device.

Abstract: A video processing device includes a data segmentation generator that receives a domain selection, n, and that segments input A/V data into n data blocks. An encryption processing device receives an encryption depth selection, k, and a range selection, m, and sequentially encrypts each of the n data blocks m times using k different keys to generate n encrypted data blocks. An output formatter generates encrypted A/V data from the n encrypted data blocks.

Abstract: A system for processing a video signal into a processed video signal includes a pattern recognition module for detecting a face in the image sequence, based on coding feedback data, and generating pattern recognition data in response thereto, wherein the pattern recognition data indicates the pattern of interest. A video codec generates the processed video signal and generates the coding feedback data in conjunction with the processing of the image sequence.

Abstract: A processing system includes a memory module that stores an electronic program guide (EPG) authoring application. A processing module executes the EPG authoring application including a graphical user interface that responds to input from an end user. The EPG authoring application creates EPG configuration data to configure an EPG application of a client device associated with the end user.

Abstract: A device for use in conjunction with a video processing device includes an adaptive filter for processing input pictures into selectively filtered pictures, based on a filter motion data. A deinterlacer selectively interpolates the selectively filtered pictures into selectively deinterlaced pictures, based on deinterlace motion data. A motion detector generates the filter motion data and the deinterlace motion data, based on detecting motion in the input pictures.

Abstract: A processing device includes a memory and a processor that generates a plurality of read commands for reading read data from the memory and a plurality of write commands for writing write data to the memory. A prefetch memory interface prefetches prefetch data to a prefetch buffer, retrieves the read data from the prefetch buffer when the read data is included in the prefetch buffer, and retrieves the read data from the memory when the read data is not included in the prefetch buffer, wherein the prefetch buffer is managed via a linked list.

Abstract: A pixel interpolation process is based on detection of a potential edge in proximity to a pixel being estimated, and the angle thereof. The potential edge and its angle is determined based on filtering of offset or overlapping sets of lines from a pixel window centered around the pixel being estimated and then cross-correlating the filter results. The highest value in the correlation result values represents a potential edge in proximity to the pixel being estimated and the index of the highest value represents the angle of the potential edge. This information is used in conjunction with other information from the cross-correlation and analysis of the differences between pixels in proximity to verify the validity of the potential edge. If determined to be valid, a diagonal interpolation based on the edge and its angle is used to estimate the pixel value of the pixel. Otherwise, an alternate interpolation process, such as vertical interpolation, is used to estimate the pixel value for the pixel.

Abstract: A device for use in conjunction with a video processing device includes an adaptive filter for processing input pictures into selectively filtered pictures, based on a filter motion data. A deinterlacer selectively interpolates the selectively filtered pictures into selectively deinterlaced pictures, based on deinterlace motion data. A motion detector generates the filter motion data and the deinterlace motion data, based on detecting motion in the input pictures.

Abstract: A device for use in conjunction with a video processing device includes a deinterlacer that selectively interpolates a plurality of pictures into a plurality of selectively deinterlaced pictures, based on deinterlace motion data. A motion detector generates the deinterlace motion data for a picture of the plurality of pictures. The deinterlace motion data is generated based on instantaneous deinterlace motion data generated by comparing an amount of motion for individual pixels of the picture of the plurality of pictures to a motion detection threshold, and also based on historic motion data that considers motion for at least three adjacent pictures of the plurality of pictures having the same odd/even polarity.

Abstract: A device for use in conjunction with a video processing device includes an adaptive filter for processing input pictures into selectively filtered pictures, based on a filter motion data. A deinterlacer selectively interpolates the selectively filtered pictures into selectively deinterlaced pictures, based on deinterlace motion data. A motion detector generates the filter motion data and the deinterlace motion data, based on detecting motion in the input pictures.

Abstract: A method and system is described by which a graphics engine can be shared to implement the functions of video encoder, such as video compression, to generate motion vectors.

Abstract: A mixed-voltage circuit employs a higher-voltage transistor in series connection with a lower-voltage transistor. To protect the lower-voltage transistor from transient overvoltage events, a series of one or more diodes is connected between the current terminals (i.e., the source and drain terminals) of the lower-voltage transistor so as to limit the voltage across the lower-voltage transistor. This diode protection mechanism also may be provided between the gate terminal and a current terminal of the lower-voltage transistor so as to protect against an overvoltage event at the gate of the lower-voltage transistor. In this manner, the mixed-voltage circuit can provide the performance benefits of mixed use of lower-voltage and higher-voltage transistors while reducing the risk of damaging the lower-voltage transistors due to the use of the higher-voltage power supply needed for operation of the mixed-voltage circuit.

Abstract: A partition subset selection module selects a subset of available partitions for a macroblock pair of the plurality of macroblock pairs, based on motion search motion vectors generated by a motion search section, and further based on a macroblock adaptive frame and field indicator. A motion refinement module generates refined motion vectors for the macroblock pair, based on the subset of available partitions for a macroblock pair.

Abstract: A first video picture is translated based upon a first translation matrix to adjust a contrast of the first video image. A second translation matrix is determined based upon a first histogram of a second video picture. A third translation matrix is determined based upon the first translation matrix and the second translation matrix, and the video picture is translated based upon the third translation matrix. The translation matrix can be determined using a histogram that has been adjusted using a clipped histogram equalization technique.

Abstract: A device includes a key store memory that stores one or more cryptographic keys. A rule set memory stores a set of rules for accessing the cryptographic keys. A key store arbitration module grants access to the cryptographic keys in accordance with the set of rules. The device can be used in conjunction with a key ladder. The device can include a one-time programmable memory and a load module that transfers the cryptographic keys from the one one-time programmable memory to the key store memory and the set of rules to the rule set memory. A validation module can validate the cryptographic keys and the set of rules stored in the key store and rule set memories, based on a signature defined by a signature rule.

Abstract: An apparatus generally having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) divide a plain text into at least three input blocks and (ii) generate at least three scrambled blocks by scrambling the input blocks using a first cipher process. The first cipher process may be configured such that a first of the input blocks does not affect the generation of a last scrambled block. The second circuit may be configured to (i) generate at least three output blocks by de-scrambling the scrambled blocks using a second cipher process and (ii) reconstruct the plain text from the output blocks. The second cipher process may be configured such that a first of the scrambled blocks affects the generation of all of the output blocks.

Abstract: A modular circuit emulation system includes a global clock generator that generates a plurality of clock signals. A plurality of emulation boards each include at least one programmable circuit and a clock buffer. The clock buffer generates at least one synchronized clock signal for clocking the programmable circuit or circuits, based on at least one of the plurality of global clock signals.

Abstract: A system for searching at least one video signal based on an input text string includes a video processing system that processes the at least one video signal by decoding the at least one video signal, encoding the at least one video signal or transcoding the at least one video signal. The video processing system generates a plurality of text strings that describe the video signal in conjunction with the processing. A memory stores a searchable index that includes the plurality of text strings. A search module identifies at least one matching video of the at least one video signal by comparing the input text string to the plurality of text strings of the searchable index.

Abstract: A system for processing a video signal into a processed video signal includes a pattern recognition module for detecting a pattern of interest in the image sequence based on coding feedback data and generating pattern recognition data in response thereto. A video codec generates the processed video signal and generates the coding feedback data in conjunction with the processing of the image sequence.