Abstract: Herein disclosed is a semiconductor integrated circuit for testing test data of two kinds of non-inverted and inverted statuses of all bits by itself with a prospective data of one kind to compress and output the test results. The semiconductor integrated circuit includes a decide circuit 25 for deciding a first status, in which the prospective data latched by a pattern register and the read data of a memory cell array are coincident, a second status, in which the read data is coincident with the logically inverted data of the prospective data, and a third statuses other than the first and second statuses through an exclusive OR gate to generate signals of 2 bits capable of discriminating the individual statuses. These statuses are informed to the outside of the semiconductor integrated circuit in accordance with high- and low-levels and a high-impedance.

Abstract: There is provided a semiconductor integrated circuit device having bipolar transistors each composed of an emitter region, base region, and collector region arranged vertically on a semiconductor substrate, said collector region having a plane figure, with the square corners thereof cut off. To be concrete, the buried collector region having a high concentration of impurity has its square corners cut off and the base region formed on the major surface of the epitaxial layer formed on said buried collector region has also its square corners cut off. The bipolar transistor having such a plane figure has a reduced parasitic capacity and an increased operating speed. A manufacturing method is also provided capable of producing a highly reliable groove isolation structure with a low dielectric constant.

Abstract: The semiconductor memory is facilitated with control circuitry for effecting plural self-refresh modes having respectively different refresh periods. The plural self-refresh modes are typified by a PS (pseudo) refresh mode which is applied when the memory is in the nonselected state for a comparatively long period of time, such as in the state in which memory backup is being facilitated, and by a VS (virtual) refresh mode in which the refreshing operation of the memory cells is effected intermittently during the intervals of memory accessings. The pseudo refresh mode has a longer refresh time period than the virtual refresh mode. The control circuitry also has counter circuits for the generating of refresh address signals in accordance with a first timing signal indicative of a pseudo refresh mode and a second timing signal indicative of a virtual refresh mode, the latter timing signal being a higher frequency signal.

Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.

Abstract: Disclosed is a semiconductor integrated circuit device having a plurality of fine memory devices and its fabrication method, and particularly to a semiconductor integrated circuit device capable of suppressing the kink current disturbance of MOS transistors without reducing the junction characteristic of the diffusion layers and its fabrication method. In this device, an angle between the lower surface of each edge of a field oxide formed in an environmental device area, i.e. a peripheral circuit area, and the main surface of a semiconductor substrate is smaller than an angle between the lower surface of each edge of a field oxide formed in a memory cell area and the main surface of the semiconductor substrate.

Abstract: Two paths for receiving the outputs of a logic select circuit LOGS are individually equipped in a symmetric manner with output MOSFETs Q52 and Q53, feedback MOSFETs Q54 and Q55 and isolating MOSFETs Q56 and Q57, the paired of which have conduction types different from each other. Negative erasing Vee voltage and programming Vpp voltage to be fed to the paths through the feedback MOSFETs are prevented without fail from being transmitted to a logic select circuit by the paired isolating MOSFETs of the different conduction types. As the elements for selecting the positive or negative logic output of the logic select circuit, CMOS transfer gates TG1 and TG2 can be adopted to maximize the amplitude of the output logic signal of the logic select circuit with respect to an operating power.

Abstract: A leadframe according to this invention is formed by bonding a single leadframe with a substrate using adhesive film or double-sided adhesive resin film, which is divided and attached to two or more predetermined points between them. This reduces the quantity of gas or contaminants generated from adhesives. Also, this results in the reduction of the stress generated during heat treatment of the leadframe and also in the elimination of warping of the lead frame due to thermal stress. Cracking does not occur on the resin because resin is removed easily and assuredly, and no air is left behind. This contributes to high reliability and increased productivity. The lead frame is further formed by bonding a plurality of metal substrates of different materials to single leadframe. This through more stable thermal behavior high reliability.

Abstract: A plurality of memory cells have their sources and drains formed integrally with n.sup.+ -buried layers acting as first data lines in a semiconductor substrate. The n.sup.+ -buried layers are connected with second data lines through transfer MISFETs. These transfer MISFETs have their gates made of the same layer of polycrystalline silicon as that of the floating gates of memory cells and are shunted at each predetermined number of bits by Al lines having a lower resistance than that of the polycrystalline silicon.

Abstract: Each internal circuit of a semiconductor integrated circuit operates at both a relatively high operating voltage having a predetermined allowable range and a relatively low operating voltage also having a predetermined allowable range. The operating voltage is externally supplied. Operating conditions of the semiconductor integrated circuit are individually set restrictive to the relatively high operating voltage having a predetermined allowable range and to the relatively low operating voltage having a predetermined allowable range. The semiconductor integrated circuit is operable selectively at these operating voltages. Since the internal circuits are operated at two operating voltages, an arrangement of internal circuits can be simplified while the semiconductor integrated circuit is concurrently usable in not only the conventional system but also a low-voltage one.

Abstract: When the data of a mask pattern of a phase shift mask is to be made, the pattern data is separated into a real pattern data layer having the data of real patterns and a phase shift pattern data layer having the data of phase shift patterns. After this, it is verified whether or not the mask pattern satisfies the regulation of the gap of in-phase patterns, in which lights having transmitted through patterns adjacent to each other are in phase. It is also verified whether or not the mask pattern satisfies the regulation of the gap of out-of-phase patterns, in which lights having transmitted through patterns adjacent to each other are out of phase.

Abstract: A semiconductor integrated circuit device constituted by a plurality of sets each of which having a pair of memory mats and each memory mat having a plurality of memory cells arranged in a matrix and a sense amplifier, I/O lines for transmitting signals provided by the sense amplifiers, selecting circuitry for selecting either a condition for sending out the signals provided by the sense amplifiers on the I/O lines or a condition for not sending out the same on the I/O lines, and Y-selection lines for transmitting the selection signals. A decoder connected with selection is disposed substantially at the middle of the Y-selection lines. X- and Y-address buffers are disposed close to each other nearer to the center of the chip than X- and Y-redundant circuits. A reference voltage generating circuit is disposed nearer to the edge of the chip than an output buffer circuit. A relief selecting circuit of each memory mat is formed adjacent to a redundant line selecting circuits included in the same memory mat.

Abstract: Compressor/expander circuits which are built in a common semiconductor substrate along with a random access memory unit function so as to realize compression/expansion processes merely through the internal data transfer controls between the circuits and the random access memory unit as based on built-in control unit. This endows the temporary storage of data and the compression/expansion processes hereof with continuities, and achieves higher speeds for the compression/expansion processes.

Abstract: A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed.

Abstract: One object of the present invention is to provide the reduced projection exposure method which enables the exposure of various and fine patterns in manufacturing process of semiconductor devices or semiconductor integrated circuit devices. Structure of the present invention to attain the above object is to carry out the reduced projection exposure using a phase shift mask provided with a prescribed correction pattern on the end of the mask pattern domain of a constant mode or the boundary of the mask pattern domain of plural modes. According to this structure, as the end effects etc. are canceled by the correction pattern, the various and fine patterns can be exposed.

Abstract: A semiconductor memory device having a plurality of nonvolatile memory devices or elements disposed in a matrix arrangement as one or more memory arrays is provided with a write operation and a verify mode which is automatically implemented when the write operation of the memory device ends. In connection with this, an auto-verify function is set in an internal circuit associated with the memory in accordance with a predetermined control signal and wherein a read mode subsequent to the write operation is implemented. During the auto-verify function, the read mode is implemented by effecting a data comparison circuit, such as an exclusive-OR logic circuit, which performs a coincidence/non-coincidence operation comparing the write data and the read data.

Abstract: A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

Abstract: A semiconductor circuit device includes a multi-layered substrate comprising a plurality of signal lines sandwiched between a power source line and a ground line, with insulation layers formed therebetween to reduce fluctuation of a ground line potential at the time of simultaneous switching of the signal lines and to increase the operational speed. The signal lines provides bidirectional current paths and is disposed between the current source line and the ground line. The multi-layered substrate is formed around a semiconductor pellet. Electrode pads are formed on the insulation layer over the ground line on the same level as the signal lines and generally on the same level as the main surface of the semiconductor pellet where electrodes pads are formed. Bonding wires are used to electrically connect the electrode pads on the pellet and the electrodes formed on the insulation layer.

Abstract: In a voltage converter provided in a semiconductor memory and supplying an internal supply voltage to a circuit in the semiconductor memory, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. The voltage converter includes MOS transistors and differential amplifiers interconnected with one another, as well as voltage dividing means. The memory also includes a word line booster for boosting the internal supply voltage.

Abstract: In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.

Abstract: Herein disclosed is a semiconductor integrated circuit device which has a memory array or a memory mat formed of memory cells arranged regularly in a matrix shape. At the end portion or inside of the memory array or memory cell in the region of the device where the patterning of the memory cells is discontinued or interrupted, the shape of an element isolating insulating film, which is formed for regulating the memory cells having pattern interruptions, is made substantially identical to the shape of the element isolating insulating film for regulating the memory cells in the region of the device where the patternings of the memory cells are of an uninterrupted regular form. In the location on the chip front face where the regular patterns associated with the memory area are discontinued, there is formed a dummy pattern having a shape made substantially identical to that of a gate electrode arranged at the end portion of the location where the regular patterns are interrupted.