Abstract: A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor.

Abstract: A data storage device for storing data strings each including units of data has a plurality of memory sections each for storing therein a table, a plurality of processor elements one provided for each of the tables and a controlling unit having an internal memory in which data strings are stored. The table contains a plurality of records each including a unit of data, a first index data representative of the number of units of data of a data string which the unit of data constitutes and a second index data unique to each individual data string. The processor elements access in parallel their associated tables under control of the control unit for data storage and data retrieval. The first and index data are generated by the controller for the purpose of data storage.

Abstract: In a microprocessor, a minimum instruction code length is set to a predetermined number of bits (e.g. one byte) length. One feature of the invention is that an instruction set which can selectively expand the instruction code length at a unit of the predetermined number of bits is used. Another feature is that an operand addressing mode and a type of operation for an operand are designated by separate predetermined number of code bits which are coded in a common coding scheme so that an instruction decoder is shared by those codes.

Abstract: Disclosed is a preferable method for producing an avalanche photo diode in which an impurity-doped region having a relatively high concentration and a step-like distribution has a step portion in another impurity-doped region having a relatively low concentration and a gradational distribution so that the circumferential portion of the high concentration region is made shallow in comparison with the central portion of the same, the step portion having a shape so that the radius of curvature thereof varies continuously.

Abstract: A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed.

Abstract: A voltage comparator is provided including a differential amplifier, first, second and third switches, and first and second capacitors. A fourth switch is connected in series between the second and third switches and an input terminal of the differential amplifier. A first input voltage is sampled and held at the first capacitor through the first switch and at the second capacitor through the second and fourth switches, respectively. Thereafter, since the third switch is turned on and the fourth switch is turned off, the first input voltage is sampled and held at the input capacitor of the differential amplifier. Thereafter, the third switch is turned off and the fourth switch turned on. As a result, an on and off operation of the fourth switch is controlled so that a second input voltage which has been sampled at the second capacitor immediately before the switch is turned off is applied to the input capacitor of the differential amplifier.

Abstract: An ECL circuit wherein a current switch and an emitter follower are coupled, is so constructed that, in a standby mode, the current switch has its current cut off or rendered smaller than in an operating mode. In addition, the ECL circuit comprises means for decoupling a load resistance of the current switch and a base of the emitter follower in the case of cutting off the current of the current switch, or means for increasing the load resistance of the current switch in the case of rendering the current of the current switch smaller. The semiconductor circuit of the present invention can reduce the power consumption of the ECL circuit and can suppress fluctuations in the voltage levels of the outputs of the ECL circuit.

Abstract: Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.

Abstract: A semiconductor logic device having arrays of logic elements and chains of logic cells alternately arranged in a direction substantially perpendicular to the direction of the chains of logic cells in a surface portion of a semiconductor substrate. Each of the logic element arrays has input and output leads extending from the array in the above-mentioned direction substantially perpendicular to the direction of the chains of logic cells so that each of said logic cell chains is in an electrical connection with two adjacent logic element arrays via the input and output leads.

Abstract: In a single chip processor which can be provided with an extended program memory, a high-speed access can be executed without being restricted by the access time for the external program memory when an internal program memory is employed, by varying the effective instruction cycle, and thus a high-speed processing performance for a single chip processor of a stored program type can be attained.

Abstract: A semiconductor device comprising a plurality of circuits driven by at least one external power source, and at least one voltage converter transforming the voltage of the external power source into another voltage. At least a part of the plurality of circuits are driven by the output voltage of the at least one voltage converter, which is provided with a controller for controlling its load driving power, corresponding to the operation of the part of the plurality of circuits. The voltage converter includes a voltage limiter which is used exclusively for each of the different natures of the loads, and its operation and load driving power are controlled, depending on the operations of each of the loads.

Abstract: A plurality of external input information are added to a selecting circuit. The output of the selecting circuit is fed back as one of the external input information to the selecting circuit. The input signal groups are decoded, and are produced as control signals to specify the external input information in synchronism with clock signals. When the input select signal groups have the non-selection mode, the output that is fed back is necessarily selected.

Abstract: Interconnections interconnecting terminals to be connected by routings are dissolved into two-terminal interconnections and it is determined to which kind of terminals the terminals of each two-terminal interconnection belong, among connected diffusion layer, separated diffusion layer and gate. The interconnections are classified into groups by the combination of the kind of two terminals for each interconnection. The respective groups of interconnections are routed in the channel on the field effect transistor row according to a predetermined order of groups.

Abstract: An echo suppressor for a communication system wherein a signal sent to a transmitting line is returned to a receiving line with some delay. The suppressor comprises an attenuator for attenuating the amplitude of a received speech signal. The transmitting speech signal amplitude level is compared to the amplitude of a receiving speech signal, and according to the result obtained, a signal for controlling the signal attenuation of the attenuator is generated. The delay time, until the attenuation control signal operates on the attenuator according to a change in the amplitude level of the receiving speech signal, is controlled. The controlled delay time is normally held at a predetermined maximum value, and is minimized when a change in amplitude of the receiving speech signal indicates a beginning of speech. Thus, an echo of the speech uttered by a near end user can be suppressed without impairing a beginning of the speech signal uttered by a far end user.