Abstract: A method for minimizing signal delays caused by mismatch in length of the inner leads of a package lead frame. This is accomplished by the provision of a unique conductive trace pattern formed preferably on the top surface or else on a lower surface of an electrically-insulated, heat-conducting printed circuit board. The conductive trace pattern includes a plurality of U-shaped metallized traces. Each of the plurality of U-shaped traces have a varying length so that certain ones adjacent the inner leads at the center of the package lead frame are longer than certain ones adjacent the inner leads at the corners of the package lead frame. The conductive trace pattern and the outer leads of the package lead frame also serve to transfer heat away from a molded-plastic body encapsulating an integrated-circuit die and the package lead frame and distribute the same on the printed circuit board.

Abstract: A semiconductor integrated circuit package is provided with insulated bonding wires. The semiconductor die is mounted to a base of either a leadframe or a grid-array package. A plurality of bonding wires are bonded between bonding pads on the semiconductor die and bonding fingers at inner ends of package conductors. The bonding wires have an oxygen-plasma oxide formed thereupon to thereby provide electrically-insulated bonding wires to prevent short-circuits between adjacent bonding wires. After wire bonding of the bonding wires, the bonding wires are subjected to an oxygen plasma to form an insulating oxide on the bonding wires to prevent short-circuits with adjacent wires. The wires are aluminum or copper with an oxygen-plasma oxide formed thereupon. An oxygen-plasma oxide is simultaneously formed on a leadframe and is removed from the outer ends of the leads by blasting with a medium.

Abstract: A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a first sample page base address corresponding to a first part of a first address received from a digital signal processor (DSP). The present invention also generates a second sample page base address corresponding to a first part of a second address received from the DSP. The first and second generated sample page base addresses are then stored in respective first and second locations within a multiple entry sample page base address cache which can be accessed by the DSP without accessing a PCI bus. The first part of the first address is compared to a first part of a third address.

Abstract: A method for manufacturing arrays of field emission tips, suitable for use in field emission displays (FEDs), begins by depositing a conductive cathode layer over a substrate and then patterning the conductive cathode layer to define a set of cathode structures on which the array of tips are to be formed. A layer of a insulator material is deposited and then a layer of lift-off material is deposited. The lift-off material is capable of being selectively etched with respect to the insulator layer. The insulator material layer and lift-off material layer are patterned to define a set of apertures in which field emission tips are to be formed. Next, tip material is deposited using an unbiased high density plasma chemical vapor deposition (HDPCVD) process to form sharp field emission tips in the apertures. The HDPCVD process also forms a sacrificial layer of islands of tip material on top of the patterned layer of lift-off material.

Abstract: A method and system for latching an address for accessing a synchronous static random access memory (SRAM). A first address status signal of the SRAM is driven active, triggering an SRAM to latch the address on an address bus coupled therewith. A second address status signal is received when a valid address is placed on the address bus. In response, the first address status signal is driven inactive. This forces the last address latched by the SRAM to be the one indicated by the second address status signal. Then, a determination is made as to whether SRAM access is required based on the address placed on the bus. SRAM access may not be required if the current cycle is either non-cacheable or a miss in the SRAM. When SRAM access is not required, the first address status signal is driven active. In the alternative, when SRAM access is required, the first address status signal is maintained inactive. The first address status signal is maintained inactive until the SRAM is ready to accept a second address.

Abstract: The present invention, generally speaking, provides for pin sharing between two or more disparate memory devices, a dynamic memory device such as a CD ROM drive or the like and a static memory device such as a ROM integrated circuit. In accordance with one embodiment of the invention, a common set of pins of an integrated circuit are used to interface to a plurality of different information storage device including both a dynamic storage device and static storage device by, in a first mode, using a first subset of the common set of pins to carry data information for one of the devices and, in a second mode, using the first subset of pins to carry address information for another one of the devices. In accordance with another embodiment of the invention, an integrated circuit includes a set of I/O pins, a multiplexer coupled to the set of I/O pins, and multiple device controllers coupled to the multiplexer, including both a dynamic storage device controller and a static storage device controller.

Abstract: The present invention comprises a cache based scan matrix keyboard controller system. The cache based scan matrix keyboard controller system includes a plurality of keys on a keyboard adapted to signal when a key is activated. The cache based scan matrix keyboard controller system also includes a cache memory component and a state machine. The cache memory component stores information regarding the keys for a period of time. The state machine is adapted to interpret the information in the cache memory component to efficiently control said keyboard in a manner that minimizes reliance on CPU processing and reduces expenditure of design, manufacturing and operating resources.

Abstract: A semiconductor integrated circuit package is provided with insulated bonding wires. The semiconductor die is mounted to a base of either a leadframe or a grid-array package. A plurality of bonding wires are bonded between bonding pads on the semiconductor die and bonding fingers at inner ends of package conductors. The bonding wires have an oxygen-plasma oxide formed thereupon to thereby provide electrically-insulated bonding wires to prevent short-circuits between adjacent bonding wires. After wire bonding of the bonding wires, the bonding wires are subjected to an oxygen plasma to form an insulating oxide on the bonding wires to prevent short-circuits with adjacent wires. The wires are aluminum or copper with an oxygen-plasma oxide formed thereupon. An oxygen-plasma oxide is simultaneously formed on a leadframe and is removed from the outer ends of the leads by blasting with a medium.

Abstract: A circuit arrangement utilizes a common bus for functional operations of logic circuits and for scan testing the logic circuits. In one embodiment, input/output ports and scan test ports of the logic circuits are switchably coupled to a bus. For functionally testing the logic circuits, a predetermined command transmitted over the bus causes the scan test ports to be coupled to the bus and the input/output ports to be decoupled from the bus. Test data may then be transmitted to and from the logic circuits via the bus. When testing is complete, a second predetermined command transmitted over the bus causes the scan test ports to be decoupled from the bus and the input/output ports to be coupled to the bus.

Abstract: A circuit arrangement on a handset for monitoring changes in the system parameters of a personal handyphone system by hardware checking the broadcasting reception indication (BRI) pattern. The circuit arrangement includes a memory portion for storing the previous BRI pattern received at the circuit arrangement, and an interrupt generator for comparing the stored previous BRI pattern with a current BRI pattern and for generating an interrupt to activate the handset processor when the previous BRI pattern differs from the current BRI pattern.

Abstract: The optimization process of the present invention replaces the successive delay table generation approach of the prior art with one that minimizes delay table size by generating only those indices sufficient to satisfy the error limits prescribed. This is accomplished by generating only portions of the delay table by reducing the maximum load/ramp point for each generated portion until such time as the error percentage limit is not exceeded. The load/ramp indices for the generated delay tables are those defined for the interpolation comparison table. These non-linearly distributed indices force a greater indexing range within the higher load/ramp regions, where relative interpolation error percentage are not as great as those within the lower regions. Within the present invention, the maximum load/ramp point of the last optimized portion becomes the minimum of the next portion, while the maximum load/ramp of the interpolation table becomes the next max point.

Abstract: A method is used to detect a location of contaminant entry in a processing fluid production and distribution system. A wafer is placed in a clean container. The clean container is connected to a test point within the processing fluid production and distribution system. Processing fluid from the test point of the processing fluid production and distribution system is allowed to flow through the clean container. The wafer is dried. The wafer is then tested for the existence of contaminants.

Abstract: A semiconductor die assembly of this invention includes a lead system in which the leads are arranged in a radial pattern. That is, in a group of leads associated with a single side of a semiconductor die, leads which are furthest from the middle are most angled from the perpendicular. The semiconductor die includes an outer row of bond pads which are located proximate to the edge of the semiconductor die and an inner row of bond pads, parallel to the first row and located toward the interior of the semiconductor die surface. In one embodiment, one of the rows of bond pads is regularly spaced, while the other row of bond pads is variably spaced.

Abstract: A method of forming sharp oxide peaks on the surface of a semiconductor wafer for the purpose of conditioning polishing pads used during a Chemical Mechanical Polishing process is disclosed. In order to create oxide peaks on the surface of a wafer, additional elements are added to a trace layer of the wafer. An oxide layer is deposited over the additional elements using an Electron Cyclotron Resonance Chemical Vapor Deposition process, which includes a sputtering step, in order to create sharp peaks in the oxide layer over the additional lines. In some embodiments, the additional elements may be formed from a multiplicity of rectangular blocks over which pyramid-like oxide peaks are created. In others, they may be formed from a multiplicity of rectangular blocks connected by narrow lines over which pyramid-like oxide peaks and knife-edged peaks, respectively, are created.

Abstract: The present invention, generally speaking, provides compact ROM layouts for trace or via-programmable (e.g., metal programmable) using transistor stacks. A number of field effect transistors (for example, eight) are coupled in series. For a particular transistor, a logic zero is programmed by forming a metal trace between the source and drain of the transistor. To read out the value of a particular bit, a logic zero is applied to the gate of the corresponding transistor. Logic ones are applied to the gates of the remaining transistors in the stack. A logic one precharge signal is applied to the top and bottom of the stack. A logic zero is then applied to the bottom of the stack. The logic zero reaches a sense amplifier coupled to the top of the transistor stack only if there is a short circuit across the transistor being read, indicating a logic zero bit value. Otherwise, the precharged logic one condition remains.

Abstract: A method and system that enables a portable station within the personal handy phone system (PHS) to utilize the preamble field of the communication interface to contain extended common access channel field information while optimizing power consumption. The present invention can operate within a cell station of the PHS. The present invention empowers a portable station to identify the type of data contained within the preamble field. A predetermined number of data bits are extracted from the beginning of the preamble field of an incoming data frame received by a portable station. The present invention determines if the extracted data bits are identical to a predetermined data bit pattern. If the extracted data bits are identical to the data bit pattern, the portable station is directed to treat the data contained within the preamble field as the standardized preamble of the PHS by not storing it within memory and not performing a cyclic redundancy check (CRC) on it.

Abstract: A semiconductor integrated circuit package is provided with insulated bonding wires. The semiconductor die is mounted to a base of either a leadframe or a grid-array package. A plurality of bonding wires are bonded between bonding pads on the semiconductor die and bonding fingers at inner ends of package conductors. The bonding wires have a PECVD S.sub.i O.sub.2 layer formed thereupon to thereby provide electrically-insulated bonding wires to prevent short-circuits between adjacent bonding wires. After wire bonding of the bonding wires, an insulating PECVD S.sub.i O.sub.2 layer is formed on the bonding wires to prevent short-circuits with adjacent wires. An S.sub.i O.sub.2 layer is simultaneously formed on a leadframe and is removed from the outer ends of the leads by blasting with a medium.

Abstract: The present invention provides for a hexagonal semiconductor die, semiconductor substrates and methods of forming a semiconductor die. One embodiment of the present invention provides a method of forming a semiconductor die comprising: providing a semiconductor wafer; forming an array of regular hexagonal dies upon the wafer, the array being formed in a two-dimensional honeycomb configuration; forming circuitry upon individual ones of the hexagonal dies; separating the hexagonal dies by laser cutting; and attaching a plurality of electrical contacts to the circuitry of individual ones of the hexagonal dies.

Abstract: The present invention includes differential devices and methods of protecting a semiconductor device. One aspect of the present invention provides a differential device adapted to be coupled to a ground connection, the differential device comprising: a first interconnect; a second interconnect; a common diffusion region; a first MOS device coupled with the common diffusion region and the first interconnect; a second MOS device coupled with the common diffusion region and the second interconnect; and a tail MOS device coupled with the common diffusion region and adapted to be coupled to a ground connection.

Abstract: A method for transferring data is performed by a first input/output device in order to perform a data transaction with a host device. The first input/output device receives a first data transaction request from the host device. The first input/output device stops the first data transaction. The first input/output device then requests a data second transaction with a second input/output device and asserts a request signal. The first input output device continuously asserts the request signal even when receiving a stop signal from the second input/output device. The first input/output device retries the second data transaction with the second input/output while continuously asserting the request signal. Upon completing the second data transaction with the second input/output device, the first input/output device releases the request signal. The first input/output device then completes the data transfer with the host device.