Abstract: A method and system that enables real-time peripheral devices to be connected to a computer system utilizing Universal Serial Bus architecture. The present invention empowers the computer system to perform an accurate determination of the moment in time a predetermined event occurred within a real-time peripheral device by utilizing the start of frame pulse transmitted from a USB host controller to peripheral devices connected to it. When a predetermined event occurs within a peripheral device, a first timer within the peripheral device starts incrementing to determine the amount of time that elapses until the next start of frame occurs. Once the next start of frame occurs, the first timer stops incrementing and stores the time before start of frame value. Every start of frame pulse causes a second timer located within the USB host controller to start incrementing.

Abstract: A method for protecting proprietary information. In one embodiment, the present invention is comprised of the steps of inserting a call to license management code within the proprietary information to be protected. The call to the license management code is inserted into the proprietary information such that at least one statement critical to the function of the proprietary information is embedded within the call to the license management code. Next, the present invention encrypts the call to the license management code having the at least one statement critical to the function of the proprietary information embedded therein. In so doing, the present invention produces a first encrypted code such that removal of the first encrypted code results in the removal of the at least one statement critical to the function of the proprietary information. The present invention then stores the first encrypted code and the proprietary information in computer readable memory.

Abstract: Disclosed is a capacitive structure and method for making the capacitive structure for suppressing inductive noise produced by high performance device power supplies. The capacitive structure includes a trench having a bottom surface and respective walls that are integral with the bottom surface. The trench is defined in a semiconductor substrate and is configured to isolate at least one transistor active area from another transistor active area. The structure further includes an oxide layer that is defined along the bottom surface and the respective walls of the trench, such that a channel is defined within the trench between the oxide layer that is defined along the bottom surface and the respective walls. The structure also includes a conductive polysilicon layer that is defined within the channel and is within the trench. The conductive polysilicon layer defines a conductive electrode that is separated from the semiconductor substrate by a thickness of the oxide layer.

Abstract: A plasma confinement ring comprising a first generally planar surface; a second generally planar surface; an aperture extending between the first and second surfaces, the aperture including an annular surface, and a curved surface extending between the annular surface and the first planar surface.

Abstract: In the manufacture of an integrated circuit, contaminated oxide is replaced by relatively pure oxide using the following steps. First, a partially manufactured integrated circuit is bathed in an aqueous solution of hydrogen peroxide and ammonium hydroxide to oxidize organic materials and weaken bonds of metal contaminants to the integrated circuit substrate. Second, an aqueous rinse removes the oxidized organic materials and metal contaminants. Third, the integrated circuit is bathed in an aqueous solution of hydrogen fluoride and nitric acid. The hydrogen fluroide etches the contaminated oxide; the nitric acid combines with calcium and metal contaminants freed as the oxide is etched. The resulting nitride byproducts are highly soluble and easily removed in the following aqueous rinse. A drying step removes rinse water from the integrated circuit. Finally, an oxide formation step provides a relatively pure oxide layer.

Abstract: A microprocessor includes a programmable instruction trap that can be used to deimplement instructions that lead to erroneous results. Upon discovery of a logic design defect, a microprocessor manufacturer can distribute an updated exception handler and a patch for a boot sequence. Upon power up, the boot sequence programs instructions to be deimplemented into a trap list. Each received instruction (issued by an application program, for example) not matching any listed instruction is executed in due course. When it matches a listed deimplemented instruction, the received instruction is trapped: it is not executed but is stored in a dedicated register. An exception handler is called that can examine the trapped instruction and substitute a suitable routine. If the trapped instruction is conditionally deimplemented and the problematic conditions do not pertain, the exception handler can reissue the instruction after temporarily deactivating the trapping function.

Abstract: An integrated circuit accesses encrypted data stored in an external memory, the integrated circuit includes a main memory for storing decrypted data. A processor within the integrated circuit utilizes the decrypted data in the main memory. A soft secure memory management unit (SMMU), within the integrated circuit, monitors data accesses by the processor. The soft SMMU signals the processor when the processor attempts to access first data which is not within the decrypted data in the main memory but is within the encrypted data stored in the external memory. When the soft SMMU signals the processor, the processor oversees transfer of the first data from the external memory and oversees decryption of the first data.

Abstract: The present invention, generally speaking, takes into account the programming of a particular ROM in order to calibrate and more nearly optimize the timing of the ROMs timing unit. In one embodiment of the invention, a dummy line is less than fully populated with transistors (loads) in accordance with the greatest degree to which a corresponding actual line is populated with transistors. The dummy line may be a word line or a bit line. Furthermore, both a dummy word line and a dummy bit line may be provided. In accordance with a further embodiment of the invention, if the complement of the number of transistors in the least populated line is less than the number of transistors in the most populated line, then the memory map of the ROM may be uniformly inverted, with the output of the ROM also being inverted. Line loading and cycle time are therefore decreased, allowing for higher speed ROM operation.

Abstract: In the course of processing integrated circuits production wafers are placed within a plurality of production boats on a platform. A first baffle boat is placed at a front end of the plurality of production boats. The first baffle boat contains a first plurality of wafers made of quartz. A second baffle boat is placed at a rear end of the plurality of production boats. The second baffle boat contains a second plurality of wafers made of quartz. The plurality of production boats, the first baffle boat and the second baffle boat are placed within a processing chamber.

Abstract: A method for making a multi-layered integrated circuit structure, includes depositing a methyl doped silicon oxide layer over a substrate. SiO.sub.2 skin is deposited on the methyl doped silicon oxide layer by decreasing the flow of CH.sub.3 SiH.sub.3, increasing the flow of SiH.sub.4 and keeping the flow of H.sub.2 O.sub.2 constant for a period of time. Finally, a cap layer is deposited which adheres to the SiO.sub.2 skin.

Abstract: A die-down HBGA package includes an integrated-circuit die mounted to a substantially flat lower surface of a die-carrier/heat spreader. A flexible insulated tape layer with a central opening for the die has its upper surface adhesively fixed to the lower side of the die-carrier/heat spreader. Wire-bonding sites and a number of contact areas are connected by traces on the lower surface of the tape layer. Bonding-wire loops are connected between the wire-bonding pads on the die and the wire-bonding sites on the insulated tape layer. A rigid board, such as an epoxy or ceramic circuit board, with electrically conductive plated-through holes is fixed to the insulated flexible tape layer with adhesive. Conductive adhesive material connects the contact areas with the top surfaces of the plated-through holes. Alternatively, pins join the carrier/heat spreader and the rigid circuit board. Solder pads for solder balls are formed on the bottom surface of the printed-circuit board.

Abstract: A method and system of detecting objects displayed on a display screen is described. Each object displayed on the screen visually emits a unique identification signal. The identification signal or lack of an identification signal is detected by a detector such as a light pen or video gun and the detector transmits the identification signal on a serial bus to the display screen graphics controller thereby indicating to the controller the position on the screen at which the detector is pointed.

Abstract: A circuit arrangement for a flip chip utilizes fixed potential shield traces between various signal traces in a redistribution layer to decrease coupling impedances and crosstalk within the layer. In particular, by orienting a fixed potential shield trace between a pair of signal traces and/or between a pair of differential trace pairs, capacitive coupling between the traces is greatly reduced, thereby permitting the signal traces to be routed closer to one another than would be possible if the shield trace was omitted. Often, minimum line width and spacing design rules may be met to ensure maximum circuit density for the redistribution layer and the associated device interconnections, and without concern for excessive adverse effects due to capacitive coupling between traces in the redistribution layer.

Abstract: A pseudo-differential receiver is described which includes a bias generator circuit portion for providing a bias signal to a receiver circuit portion. The bias generator includes first and second load devices for establishing bias voltages at first and second nodes and also includes a first CMOS inverter biased by and coupled between the first and second nodes. The input of the first inverter is coupled to a reference voltage and the output of the inverter provides a bias voltage which is fed back to the gates of the first and second load devices. The biasing conditions on the first and second nodes bias the first inverter such that the threshold voltage of the first CMOS inverter is equal to the reference voltage. The biasing signal is used to bias loading devices in the receiver circuit portion. The receiver circuit portion includes loading and inverter devices that are electrically matched to the loading and inverter devices in the bias generator circuit portion.

Abstract: The present invention provides for a circuit comprising: an input operable to receive a bit pattern; a bit-operator configured to selectively transpose the bit pattern; a shifter configured to shift the bit pattern following the transposition of the bit pattern; and the bit-operator being configured to transpose the bit pattern following the shift of the bit pattern. The present invention additionally provides a barrel shifter and a method for manipulating a bit pattern.

Abstract: The present invention comprises a voltage controlled oscillator (VCO) circuit having high power supply noise rejection. The VCO circuit includes a VCO input for receiving a control voltage. A level shifter circuit is coupled to the VCO input. A first and second VCO cell are coupled to the level shifter circuit and are coupled to each other. The VCO circuit also includes a VCO output for transmitting a VCO output signal. A first source follower transistor is coupled to the first VCO cell to transmit a first voltage from the power supply to the first VCO cell. A second source follower transistor is coupled to the second VCO cell to transmit a second voltage from the power supply to the second VCO cell. A first and second load transistor are included in each VCO cell. They are directly coupled to receive the control voltage such that the VCO output signal is less sensitive to noise on the power supply and the VCO output signal remains stable.

Abstract: An automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate. In one embodiment, the present invention determines the locations of well regions on a semiconductor substrate. The present invention also determines the locations of interconnect lines on the semiconductor substrate. Next, the present invention creates a union of the location of the well regions on the semiconductor substrate and the location of the interconnect lines on the semiconductor substrate. The present invention uses this union to define allowable locations for placement of fill pattern diffusion regions on the semiconductor substrate such that the fill pattern diffusion regions are not disposed under the interconnect lines.

Abstract: A method and system for detecting objects displayed on a display screen is described. Each object displayed on the screen visually emits a unique identification signal in the form of a color signal having multiple color components. The relative peak amplitude of each color component in the color signal is detected by sampling the color signal with photo-sensors corresponding to each color component. The sampled color components are digitized and transmitted to the display screen graphics controller thereby indicating to the controller the object on the screen at which the detector is pointed.

Abstract: A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

Abstract: The invention encompasses methods of forming pairs of transistor gates. In one aspect, the invention includes a method comprising: a) defining a first region and a second region of a substrate; the first region and second region comprising a first substrate surface and a second substrate surface, respectively; b) improving a lifetime of a low voltage tolerant transistor formed proximate the first substrate surface by cleaning the first substrate surface with a first mixture comprising hydrofluoric acid and hydrochloric acid; c) forming a first transistor gate over the first substrate region and incorporating the first transistor gate into the low-voltage tolerant transistor; and d) forming a second transistor gate over the second substrate region and incorporating the second transistor rate into a high-voltage tolerant transistor.