Abstract: A semiconductor device isolating structure and method for forming such a structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall extending to the bottom surface of the trench, and a second sidewall extending to the bottom surface of the trench. Furthermore, the trench of the present invention also has a first field oxide region formed proximate to the interface of the first sidewall and the top surface of the semiconductor substrate, and a second field oxide region formed proximate to the interface of the second sidewall and the top surface of the semiconductor substrate.

Abstract: An apparatus and method which overcomes connectivity limitations on PCMCIA and PC-CARD95 compatible devices by reconfiguring standard PCMCIA and PC-CARD pins for additional electrical interfaces. A detection circuit in the PC-card can detect the different interfaces. Once the different interfaces are identified, the connections to the receptacles of the PC-card connector are reconfigured such that the functional assignments of the receptacles conform with the requirements of each different interface. Thus, connection between different electrical interfaces to the physical interface of a PCMCIA-compatible device, without interference between them is possible.

Abstract: A power-on-reset (POR) circuit having a reduced sized charging capacitor is described which includes a voltage detection portion, a delay portion, and a POR signal generation portion. The voltage level detection portion functions to provide a level indicator signal after the power supply has reached a predetermined voltage level. The delay portion in response to the level indicator signal indicating that the power supply is greater than or equal to the predetermined voltage level charges a chargeable node to an inverter trip point voltage level in a predetermined delay time interval dependent on a capacitive element and a diode connected MOS device both connected to the chargeable node. The POR signal generation portion, in response to the voltage trip point level on the chargeable node, outputs a POR signal an extended time interval afterwards.

Abstract: Disclosed is a chemical mechanical polishing system. The system includes a mechanical arm and a carrier body that is configured to be coupled to the mechanical arm. The carrier body has a recessed portion for retaining a semiconductor wafer. The recessed portion has a carrier film that is in direct contact with a back side of the semiconductor wafer. The system further includes a plurality of pressure rings that are defined in the carrier body, such that the plurality of pressure rings are in direct contact with the carrier film. Each of the plurality of pressure rings are used to apply a selected pressure to the carrier film, such that the carrier film produces a back pressure against the back side of the semiconductor wafer. The back pressure is configured to be consistent with the selected pressure that is applied to each of the plurality of pressure rings.

Abstract: A low-noise output buffer in accordance with the present invention includes pre-driver circuitry coupled to core circuitry of an integrated circuit, output circuitry having a variable drive level that is responsive to the pre-driver output signal and powered by a first power supply, and noise reduction control circuitry coupled to the first power supply. The noise reduction control circuitry is powered by a second power supply which has less noise than the first power supply, and is arranged to develop a control signal that is coupled to the output circuitry to modify the drive level of the output circuitry to counteract noise detected on the first power supply. In some embodiments, the noise reduction control circuitry includes a first transistor and the output circuitry includes a second transistor which are arranged to form a stacked transistor pair.

Abstract: A testing apparatus including a testing plate can be used to test an electrostatic wafer chuck. A DC potential is supplied so as to produce an electrostatic force. A mechanical force is supplied to the testing plate in order to give an indication of the produced electrostatic force. By examining the DC potential and the produced electrostatic force, an electrostatic wafer chuck can be qualified or rejected before being placed into a wafer processing machine. This reduces the possibility of damage to the wafer or the wafer processing machine.

Abstract: An I/O buffer with minimized footprint; which is less susceptible to voltage spikes caused by switching noise, and which is adapted for used in a separate power bus arrangement. The buffer minimizes voltage spikes caused by switching noise by replacing the single large current surge that occurs during switching with smaller current surges at different times. This is accomplish by having two different drivers for the transitional and holding phases: a Transient Switching Circuit (TSC) and a Logic Holding Circuit (LHC). Generally, the TSC is operational to cause a change in the output signal when there is a change in the input signal. Conversely, the LHC is operational subsequent to the logic transition occurrence at the input signal to bring the output signal to the rail voltage.

Abstract: The present invention comprises a multiple functional block integrated circuit device for connecting to an external peripheral component interconnect (PCI) bus. The present invention includes an integrated circuit adapted to be coupled to an external PCI bus. The integrated circuit includes a plurality of functional blocks. Each of the plurality of functional blocks performs a function and comprises either a master functional block or a target functional block. A target bus adapted to transmit data signals is integral with the integrated circuit. The target bus is coupled to each of the plurality of functional blocks. A master bus adapted to transmit data signals is also integral with the integrated circuit. The master bus is coupled to each master functional block. A target bus interface integral with the integrated circuit is coupled to the target bus.

Abstract: The present invention comprises a smart debug interface circuit for the diagnostic testing and debugging of a software application for a programmable digital processor system. The smart debug interface circuit of the present invention includes an instruction register for coupling to an instruction bus of a programmable digital processor. The instruction register is adapted to drive instructions onto the instruction bus. The instruction register couples to the instruction bus in a parallel manner. The smart debug interface circuit of the present invention includes a data register for coupling to a data bus of the programmable digital processor. The data register is adapted to read data from the data bus and couples to the data bus in a parallel manner. The instruction register and data register are each coupled to an interface port. The interface port couples the smart debug interface circuit to a host computer system.

Abstract: A method of producing deep submicron vias is described in which a metal blanket layer is formed on a premetal dielectric and patterned to form line elements. An intermetal dielectric is then deposited over the patterned metal and chemically mechanically polished down to the top of the line elements. A second metal blanket layer is then deposited and patterned to form via studs. An intermetal dielectric is also deposited over the patterned metal via studs and polished down to the tops of the studs. The process is repeated until a multilevel integrated circuit is formed.

Abstract: A method and apparatus for determining whether an address corresponds to a cacheable memory location within a discontiguously-arranged cacheable memory space. In one embodiment, the present invention includes the following steps: First the present invention receives an address for a memory location. Next, the present invention masks a first portion of the received address with an "admask" and compares the result of the admask itself to determine whether they are a predetermined value. The present invention also masks a second portion of the received address with a "tagmask" and compares the result to the tagmask itself to determine whether they are a predetermined value. Next, the present invention generates a cacheable signal provided the first portion of the received address matches the admask and the second portion of the received address matches the tagmask. In so doing, the present invention provides a method and apparatus for caching discontiguous memory address spaces with shorter cache tags.

Abstract: Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A second dielectric layer overlying the first patterned metallization layer and the first dielectric layer. An aluminum filled via hole defined through the second dielectric layer and in contact with the first patterned metallization layer. The aluminum filled via hole has an electromigration barrier cap over a topmost portion of the aluminum filled via hole that is substantially level with the second dielectric layer. The electromigration barrier cap having a thickness of between about 500 angstroms and about 2,500 angstroms.

Abstract: The present invention comprises a chemical mechanical polishing (CMP) process for removing tungsten from the surface of a dielectric layer of a semiconductor wafer. The CMP process of the present invention removes tungsten from the surface of the dielectric layer while planarizing the dielectric surface. The system of the present invention places a wafer onto a pad of a CMP machine. The wafer includes an overlying layer of tungsten and an underlying layer of dielectric material. Slurry is dispensed onto the polishing pad and the wafer is polished by the CMP machine. The CMP machine polishes the wafer such that the CMP process has a substantially equal amount of tungsten to dielectric selectivity. This allows the CMP process to remove excess tungsten from the surface of the dielectric layer while simultaneously planarizing the dielectric layer. When the dielectric layer is sufficiently planarized and the excess tungsten has been removed, the wafer is removed from the CMP machine.

Abstract: An integrated-circuit die is attached to the top interior surface of a die-cavity formed in the underside of a heat spreader. The other side of the integrated circuit die has a number of wire-bonding pads formed thereupon. A plurality of bonding-wire loops at least some of which are completely contained within the die-cavity to allow the part of the encapsulation or lid to be as thin as possible, while still covering the bonding wires. A first portion of a insulated tape layer covers the lower outside surface of the die-carrier/heat spreader and another portion of the insulated tape layer extends inside of the die-cavity and has a number of wire-bonding sites formed thereupon. A plurality of bonding-wire loops are bonded to one of the wire-bonding pads formed on the integrated-circuit die and the wire-bonding sites formed on the insulated tape layer.

Abstract: The disclosure concerns the automatic generation of test vectors for a sequential circuit which is expressible as a finite state machine having a combinatorial part and sequential elements. A functional generation of test vectors is performed using a high level functional specification of the finite state machine. Fault simulation may be used to provide a list of possible faults not covered by the vectors generated functionally. A structural generation performed on the combinatorial part in respect of the listed faults provides test vectors for all the remaining faults except those which are due to redundancy in the circuit. The high level specification can be modified for the purpose of test generation without modifying its functionality to add transitions corresponding to the structurally generated vectors and the functional generation may be performed on the modified specification to provided a final set of test vectors.

Abstract: Methods and apparatus for coupling a digital tester to a mixed-signal device under test. In exemplary embodiments, a digital tester interface communicates with a digital tester and a device under test, and performs analog-to-digital and digital-to-analog translations between the digital tester and the device under test, so that delays associated with prior art testing systems are significantly reduced. The digital tester interface of the present invention is properly viewed as a hardware accelerator enabling quick and cost effective quality-testing of mixed-signal devices using inexpensive digital testers. Because the digital tester interface reduces per-function test time by an order of magnitude as compared to prior art systems, mixed-signal devices are more thoroughly tested and quality assurance levels are maximized at minimal additional cost.

Abstract: A method and apparatus for a reinforced leadframe to substrate attachment in a semiconductor assembly. In one embodiment, a printed circuit board having a plurality of electrically coupled electrical contact regions and wire bond areas formed thereon has a leadframe attached thereto such that each of the bonding fingers of the leadframe is coupled to a respective electrical contact region on the printed circuit board. A ribbon of B-staged epoxy is disposed on the leadframe such that the leadframe is disposed between the ribbon of B-staged epoxy and the printed circuit board. An integrated-circuit die is mounted on the printed circuit board with the bonding fingers of the leadframe peripherally surrounding the integrated circuit die. The bonding pads on the integrated-circuit die are electrically coupled to respective wire bond areas on the printed circuit board.

Abstract: The present invention relates to a system and method for implementing peripheral device bus mastering via a general purpose list processor. The system is comprised of four main elements: a bus controller, a DMA controller, a list processor, and a device controller. The system operates under two modes of operation. The two modes arise from the two distinct modules: the DMA controller and the list processor. The first mode of operation is a single buffer transfer mode which is directly compatible with a distributed DMA model. Under this mode, distributed DMA registers within the DMA controller are programmed to transfer a single contiguous buffer of data. The second mode of operation is a multiple buffer transfer mode which uses linked lists of buffer transfer descriptors to program the distributed DMA registers within the DMA controller and initiates transfers independent of software.

Abstract: A circuit arrangement for hardware checking the validity of data transmitted in a SA-field within the traffic channel of the personal handyphone system. The circuit arrangement includes a receiver for receiving control information corresponding to a SA-field, and an interrupt generator for generating an interrupt to activate the handset processor when the control information indicates the SA-field is the beginning of a series of SA-fields containing valid data.

Abstract: Line shortening and other defects in integrated circuits are measured by imprinting accuracy determinative patterns in the scribe lines or die margins of the mask field. The patterns are ideally formed in the general nature of the usual box in a box configuration with one of the boxes being specially configured to include a series of lines and spaces having narrow widths comparable to the width of the lines to be formed in the integrated circuit. The use of the narrow lines provides the box in a box configuration with the same line shortening that the circuit feature will itself experience. Small spaces between the lines permit the standard measuring equipment to locate at the ends of the lines.